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Author SHA1 Message Date
Alex Forencich
dfdf880c3a Add Stratix 10 JTAG IDs 2021-11-06 16:20:54 -07:00
Alex Forencich
7ab18f8602 Increase event FIFO depth 2021-11-06 16:14:49 -07:00
Alex Forencich
fb0f6f67f7 Remove debug code 2021-11-06 16:14:32 -07:00
Alex Forencich
f8a24d1c46 Add attributes to RAMs for proper synthesis in Quartus 2021-11-06 16:14:22 -07:00
Alex Forencich
cefb4568e7 merged changes in axi 2021-11-06 15:22:50 -07:00
Alex Forencich
b4bdfb6542 Add FIFO output register in AXI lite crossbar modules 2021-11-06 15:20:19 -07:00
Alex Forencich
0b16849b57 Add attributes to RAMs for proper synthesis in Quartus 2021-11-04 20:43:13 -07:00
Alex Forencich
aa89471cca Add bus_num port to mqnic_core_pcie 2021-11-03 21:40:19 -07:00
Alex Forencich
e0cfb0c107 merged changes in pcie 2021-11-03 20:47:25 -07:00
Alex Forencich
ce6717cbee merged changes in eth 2021-11-03 20:47:21 -07:00
Alex Forencich
9883e776c3 Parameter cleanup 2021-11-03 20:46:40 -07:00
Alex Forencich
e31345071d Add AXI RAM for example designs 2021-11-03 19:12:55 -07:00
Alex Forencich
c54dba8a94 Update readme 2021-11-03 18:38:33 -07:00
Alex Forencich
f4ffdb727d Add example design for BittWare 520N-MX 2021-11-03 18:13:40 -07:00
Alex Forencich
f2fad37273 Add example design for Stratix 10 MX development kit 2021-11-03 18:12:17 -07:00
Alex Forencich
9297c518f1 Add example design for ExaNIC X10 2021-11-03 18:10:17 -07:00
Alex Forencich
d43067a805 Add example design for fb2CG@KU15P 2021-11-03 18:09:46 -07:00
Alex Forencich
84009500a8 Add example design core logic modules 2021-11-03 01:51:10 -07:00
Alex Forencich
4cda6b07dd Update readme 2021-11-03 00:48:59 -07:00
Alex Forencich
d052264659 Add 520N-MX 10G example design 2021-11-03 00:48:06 -07:00
Alex Forencich
9e44987f60 Reorganize PHY instances 2021-11-02 23:30:48 -07:00
Alex Forencich
728e86c554 Update QSF/SDC files 2021-11-02 23:30:06 -07:00
Alex Forencich
5c5876ff1d Add PCIe interface shim for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile 2021-11-02 22:29:57 -07:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
74f32c6a59 Add missing PHY instance ports 2021-11-02 20:28:26 -07:00
Alex Forencich
0aee872452 merged changes in axis 2021-11-02 20:23:33 -07:00
Alex Forencich
96a26e7a54 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 20:22:47 -07:00
Alex Forencich
fab74d1d0f Update test durations 2021-11-02 18:29:35 -07:00
Alex Forencich
38c85a6bcd Set subsystem ID based on board, remove unnecessary configuration settings 2021-11-02 15:32:55 -07:00
Alex Forencich
d2663fd711 Print PCIe subsytem IDs 2021-11-02 14:40:32 -07:00
Alex Forencich
47a2570647 Set class code to memory controller, set subsystem ID based on board 2021-11-02 14:39:33 -07:00
Alex Forencich
ad157ca3ad Enable interrupts 2021-11-02 14:35:42 -07:00
Alex Forencich
38358ffa43 Print subsystem IDs 2021-11-02 14:35:25 -07:00
Alex Forencich
f612d88288 Rewrite op tag FIFO read in DMA engines 2021-10-31 21:57:26 -07:00
Alex Forencich
482b305913 Fix 64-bit TLP address forcing logic in generic interface model 2021-10-27 17:54:41 -07:00
Alex Forencich
545eca653c Fix kernel module coding style 2021-10-22 14:36:41 -07:00
Alex Forencich
aef59c65ec Use kernel types 2021-10-21 22:19:01 -07:00
Alex Forencich
dbd15cb60e Rework GT instances in VCU118 10G design 2021-10-21 22:16:05 -07:00
Alex Forencich
6e7109a3a0 Rework GT instances in VCU1525 10G design 2021-10-21 21:50:06 -07:00
Alex Forencich
b8eb3806a4 Rework GT instances in Alveo U280 10G design 2021-10-21 21:49:27 -07:00
Alex Forencich
bc7635e5dc Rework GT instances in Alveo U250 10G design 2021-10-21 21:48:49 -07:00
Alex Forencich
6a7a91856f Rework GT instances in Alveo U200 10G design 2021-10-21 19:58:22 -07:00
Alex Forencich
01871e46cb Rework GT instances in Alveo U50 10G design 2021-10-21 19:57:17 -07:00
Alex Forencich
6876ad4593 Rework GT instances in ZCU106 design 2021-10-21 19:00:47 -07:00
Alex Forencich
8f15664092 Rework GT instances in VCU118 design 2021-10-21 18:50:55 -07:00
Alex Forencich
cfe41e9680 Rework GT instances in ADM-PCIE-9V3 10G and 25G designs 2021-10-21 17:49:08 -07:00
Alex Forencich
2f5c15f513 Rework GT instances in fb2CG@KU15P 10G and 25G designs 2021-10-21 16:31:36 -07:00
Alex Forencich
d528949aa9 Rework GT instances in ExaNIC X10 design 2021-10-21 16:30:13 -07:00
Alex Forencich
5eca6389cf Rework GT instances in ExaNIC X25 10G and 25G designs 2021-10-21 16:29:48 -07:00
Alex Forencich
4ade485344 bits.h is not available in userspace 2021-10-21 15:38:25 -07:00