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Commit Graph

28 Commits

Author SHA1 Message Date
Alex Forencich
e06eb07621 Set PTP CDC NS width to 6 in MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:20:42 -07:00
Alex Forencich
4676296c49 Add block names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 18:51:27 -07:00
Alex Forencich
77617167fa Fix PTP TS FIFO instantiations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:34:54 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
c44e447db5 Transfer PTP information in tuser 2021-09-01 15:56:00 -07:00
Alex Forencich
77938fa422 Update MAC modules for changes in FIFO modules 2021-08-26 00:55:12 -07:00
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
909ccae151 Properly synchronize bad FCS status output 2020-12-01 14:01:15 -08:00
Alex Forencich
591527f5a7 Pass through FIFO pipeline parameters 2020-09-07 13:26:34 -07:00
Alex Forencich
ab77ac3858 Fix width 2019-07-19 18:16:07 -07:00
Alex Forencich
451db171d1 Don't leave output floating 2019-07-19 18:13:30 -07:00
Alex Forencich
16d1662d98 Add PTP timestamping infrastructure to 10G MACs 2019-07-18 23:13:46 -07:00
Alex Forencich
3bd7be44fa Update FIFO instances and update MACs to use combined FIFO adapter module 2019-07-18 16:25:49 -07:00
Alex Forencich
4da1a83052 Constant FIFO depth 2019-07-17 23:36:10 -07:00
Alex Forencich
8285f94eaa Rename tx_sync regs 2019-03-28 16:27:33 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
ad8828d5b7 Update FIFO instances 2018-10-30 11:58:06 -07:00
Alex Forencich
0aca4c7dcc Update 10G MAC to use new modules 2018-10-24 00:54:41 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
bd27156f35 AXI stream updates 2018-02-26 00:08:08 -08:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
08afe3a5d2 Synchronize MAC status signals 2015-10-09 22:51:55 -07:00
Alex Forencich
55071645fd Update async FIFO instances 2015-10-09 22:35:25 -07:00
Alex Forencich
0ecd354d7f Fix instance name 2015-06-07 22:07:04 -07:00
Alex Forencich
ec95a6055d Feed through and synchronize FIFO status signals 2015-05-12 19:12:23 -07:00
Alex Forencich
00a87b26b3 Add FIFO wrapper for 10G MAC module 2015-05-08 00:07:09 -07:00