FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-02-06 08:38:23 +08:00
Code Issues Projects Releases Wiki Activity
302 Commits 1 Branch 0 Tags
Commit Graph

205 Commits

Author SHA1 Message Date
Alex Forencich
0b5fc5b0e0 Fix off by one error 2021-09-28 01:17:57 -07:00
Alex Forencich
6c234260b2 Fix assignment type 2021-09-01 15:53:15 -07:00
Alex Forencich
6bcd96fa83 Bypass pipeline FIFO when length is zero 2021-08-27 13:54:14 -07:00
Alex Forencich
a613cc8a31 Fix alignment 2021-08-25 23:58:52 -07:00
Alex Forencich
6a030f5d5e Add axis_pipeline_fifo 2021-08-25 23:54:30 -07:00
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
Alex Forencich
0b2066abe3 Fix corner case with back-to-back single-cycle transfers 2021-08-25 19:19:30 -07:00
sungsoo.han
ceeea4b451 modify acknowledge assign 2021-08-17 16:42:26 +09:00
sungsoo.han
edaec3bd38 add LAST_ENABLE to axis_arb_mux 2021-08-17 16:00:23 +09:00
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
892ee84bff Delay command until write is acknowledged 2021-05-31 01:32:02 -07:00
Alex Forencich
3579310447 Clear active bit 2021-05-31 01:31:30 -07:00
Alex Forencich
34d5a4fed5 Add wrapper generator for RAM switch 2021-05-30 12:32:26 -07:00
Alex Forencich
16b174b490 Print addressing configuration 2021-05-30 12:19:01 -07:00
Alex Forencich
e3183862bb tkeep always active inside RAM switch 2021-05-30 12:12:10 -07:00
Alex Forencich
56a3b8fe92 Fix indexed part select error in degenerate case when M_COUNT = 1 2021-05-30 12:11:46 -07:00
Alex Forencich
8e5c4874eb Fix switch wrapper parameters 2021-05-30 12:10:04 -07:00
Alex Forencich
9d99ec0096 Update wrapper generators 2021-04-03 16:34:42 -07:00
Alex Forencich
3df18fafdd Use nonblocking assignment 2021-04-03 16:33:45 -07:00
Alex Forencich
d834e49587 Move wire declarations 2020-12-03 17:37:53 -08:00
Alex Forencich
1f9aa62639 Add wrapper generator for axis_broadcast 2020-12-03 17:31:11 -08:00
Alex Forencich
71b6b9f6f2 Prevent shift register inference 2020-09-07 18:54:18 -07:00
Alex Forencich
ede73b434a Add PIPELINE_OUTPUT parameter to FIFO adapter modules 2020-09-07 00:22:55 -07:00
Alex Forencich
2f883681d6 Add pararametrizable output pipeline to FIFOs 2020-09-07 00:14:22 -07:00
Alex Forencich
eb6861cbc4 Convert to single always block 2020-09-06 22:57:56 -07:00
Alex Forencich
c9950d56ae Rewrite full/empty logic 2020-09-06 18:28:32 -07:00
Alex Forencich
b7ed61b242 Rewrite resets 2020-09-06 17:55:10 -07:00
Alex Forencich
84cffeca5f Remove unneeded address registers 2020-09-06 17:52:41 -07:00
Alex Forencich
a7689b6772 Pipeline RAM output in RAM switch 2020-09-03 15:55:45 -07:00
Alex Forencich
ae10935a93 Rewrite priority encoder to remove recusive construction 2020-08-17 18:29:05 -07:00
Alex Forencich
4754d94736 Fix backpressure bug 2020-04-17 21:22:07 -07:00
Alex Forencich
fd1ec1690f Add sync_reset module and timing constraints 2020-03-27 18:04:04 -07:00
Alex Forencich
f9915b2f31 Refactor 2020-02-19 21:32:00 -08:00
Alex Forencich
406a3d69d1 Rework read handling 2020-02-19 21:24:15 -08:00
Alex Forencich
2876235a72 Throughput optimizations 2020-02-19 18:15:58 -08:00
Alex Forencich
52d1117753 Add AXI stream RAM switch module and testbenches 2020-02-18 01:06:14 -08:00
Alex Forencich
a9c04a4651 Fix frame FIFO drop 2019-10-24 12:08:08 -07:00
Alex Forencich
6795c25e7f Fix use before define 2019-08-09 18:05:32 -07:00
Alex Forencich
ce00df8de1 Include instance names in error messages 2019-07-25 16:30:10 -07:00
Alex Forencich
0a85a4a2aa Fix assert 2019-07-25 00:43:42 -07:00
Alex Forencich
592ae7e6a2 Change default switch addressing to use MSBs of tdest 2019-07-25 00:40:13 -07:00
Alex Forencich
76c805e416 Fix more indexing bugs 2019-07-24 15:38:49 -07:00
Alex Forencich
23b9490fac Fix switch bug 2019-07-24 15:22:35 -07:00
Alex Forencich
5f454d6c05 Update axis_switch to support default routing configurations 2019-07-24 14:20:07 -07:00
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
c091f7ed76 Add switch wrapper generator 2019-07-24 13:46:33 -07:00
Alex Forencich
b4cebd8394 Fix crosspoint wrapper generator 2019-07-24 13:44:43 -07:00
Alex Forencich
c759ff03b7 Fix default parameter 2019-07-24 11:07:17 -07:00
Alex Forencich
69de6fd2a4 Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH 2019-07-18 11:27:25 -07:00
Alex Forencich
e0a1a73ce0 Mask tdata with tkeep 2019-07-18 11:01:00 -07:00