FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
181 Commits 1 Branch 0 Tags
Commit Graph

181 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alex Forencich
e10a7ae88e Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 22:12:16 -08:00
Alex Forencich
eda769d167 Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 13:00:03 -08:00
Alex Forencich
7b2c99e731 Fix unaligned operation handling in AXI to AXIL adapter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 12:58:39 -08:00
Alex Forencich
211f674603 Fix unaligned operation handling in AXI adapter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 12:58:03 -08:00
Alex Forencich
3dc4ca92f6 Improve unaligned operation handling in AXIL adapter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 21:08:32 -08:00
Alex Forencich
f521fb6435 Update timing constraints to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-17 13:40:36 -08:00
Alex Forencich
a91e98c105 Update package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-07 20:03:34 -07:00
Alex Forencich
25912d48fe Lock package versions 2021-12-27 16:54:26 -08:00
Alex Forencich
c7ef809417 Specify min tox and venv versions 2021-12-27 16:53:49 -08:00
Alex Forencich
d11a48c94b Use available python 3 2021-12-27 16:52:07 -08:00
Alex Forencich
293cfe153c Use start_soon instead of fork 2021-12-10 18:23:39 -08:00
Alex Forencich
fbb507be82 Remove deprecated assigments 2021-11-15 14:31:28 -08:00
Alex Forencich
078bbc8f07 Fix typos 2021-11-07 17:50:23 -08:00
Alex Forencich
b4bdfb6542 Add FIFO output register in AXI lite crossbar modules 2021-11-06 15:20:19 -07:00
Alex Forencich
0b16849b57 Add attributes to RAMs for proper synthesis in Quartus 2021-11-04 20:43:13 -07:00
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
302a23209f Add missing wires 2021-10-20 13:00:44 -07:00
Alex Forencich
a6a9a2ebd8 Update readme 2021-08-29 19:16:43 -07:00
Alex Forencich
5c2c6fd2bb Add AXI lite register interface modules 2021-08-29 19:09:52 -07:00
Alex Forencich
6b108481b8 Update interconnect address handling 2021-08-26 16:48:31 -07:00
Alex Forencich
fe283eee02 Update readme 2021-08-11 01:25:42 -07:00
Alex Forencich
26534e75ce Add AXI lite crossbar module and testbench 2021-08-11 01:23:14 -07:00
Alex Forencich
39dc8662b6 Remove duplicate code 2021-08-11 01:16:02 -07:00
Alex Forencich
bf3143a79f Fix test name 2021-08-03 01:54:00 -07:00
Alex Forencich
fceea6f8d8 Add output FIFOs to DMA engines 2021-08-03 01:53:18 -07:00
Alex Forencich
ee9c719bf4 Add error reporting to DMA modules 2021-08-01 10:59:38 -07:00
Alex Forencich
db826e489b Set algorithm for pytest-split 2021-08-01 01:19:07 -07:00
Alex Forencich
2a7d190eb4 Update test durations 2021-06-03 13:48:33 -07:00
Alex Forencich
5063aeadcd Remove string parameters 2021-06-02 17:04:53 -07:00
Alex Forencich
51caad0810 Extract port counts 2021-06-01 13:22:48 -07:00
Alex Forencich
a852697707 Fix instance names in wrappers 2021-06-01 13:18:11 -07:00
Alex Forencich
9c4012f58d Reorganize timing constraints 2021-05-20 15:15:51 -07:00
Alex Forencich
314ea7dbf9 Update readme 2021-04-12 22:55:49 -07:00
Alex Forencich
a45c36e802 Update testbenches 2021-04-12 22:55:38 -07:00
Alex Forencich
bf2a779e48 Rewrite test 2021-03-24 22:00:20 -07:00
Alex Forencich
bb30f0a50f Extract parameter values from cocotb.top 2021-03-22 18:07:04 -07:00
Alex Forencich
1f3920afcc Use release version of cocotb for CI 2021-03-17 19:10:04 -07:00
Alex Forencich
be689ebb77 Update testbenches 2021-03-06 19:55:50 -08:00
Alex Forencich
0afd441eba Fix active operation count logic 2021-02-17 21:14:51 -08:00
Alex Forencich
e5f5b1c352 Remove unused regs 2021-02-17 18:30:55 -08:00
Alex Forencich
68387161d4 Track active operation count to prevent status FIFO overflow 2021-02-17 18:29:44 -08:00
Alex Forencich
83b5d30347 Rewrite resets 2021-02-17 18:06:47 -08:00
Alex Forencich
ac69ddfa22 Update github actions 2021-01-16 13:38:10 -08:00
Alex Forencich
03a78413c5 Rework sim_build output directory, fix default makefile target 2020-12-29 16:09:02 -08:00
Alex Forencich
3a59569105 Remove extraneous import 2020-12-28 18:53:00 -08:00
Alex Forencich
db58c836f6 Use absolute path to test directory 2020-12-28 18:52:47 -08:00
Alex Forencich
9ab1fb44b1 Convert send/recv to blocking 2020-12-18 16:50:50 -08:00
Alex Forencich
ca7f0131ea Remove unnecessary __init__.py files 2020-12-15 18:59:49 -08:00
Alex Forencich
be767f8ee7 Update readme 2020-12-04 16:18:28 -08:00
Alex Forencich
f8ff8a98d5 Remove README symlink 2020-12-04 16:15:32 -08:00