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343 Commits 1 Branch 0 Tags
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17 Commits

Author SHA1 Message Date
Alex Forencich
b9e0af3634 Revert change to early ready conditions for improved throughput 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-18 12:07:11 -07:00
Alex Forencich
6d4458e5cc Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:36:00 -07:00
Alex Forencich
268d0c66b8 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 12:57:41 -07:00
Alex Forencich
073d50d9dc Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 2022-03-30 16:02:17 -07:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
fd28040c40 Rename ports 2018-10-25 11:30:35 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
d16f19f67e Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter 2017-11-20 21:31:41 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
3d17cc1cee Adjust rate limiter framing logic 2015-05-12 17:58:09 -07:00
Alex Forencich
3816eb3c20 Fix parameters 2014-11-12 02:06:18 -08:00
Alex Forencich
5f14df216a Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
377ef5accb Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00