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Author SHA1 Message Date
Alex Forencich
e3f8879474 Rework GT instances in ZCU106 design 2021-10-19 18:30:35 -07:00
Alex Forencich
4ce218bc5d Rework GT instances in ADM-PCIE-9V3 designs 2021-10-19 18:29:18 -07:00
Alex Forencich
21da6f58dc Rework GT instances in Alveo U280 design 2021-10-19 18:28:10 -07:00
Alex Forencich
4fdc6408bc Rework GT instances in Alveo U50 design 2021-10-19 18:14:50 -07:00
Alex Forencich
cc4256666a Rework GT instances in Alveo U250 design 2021-10-19 17:47:15 -07:00
Alex Forencich
f11f7ecac9 Rework GT instances in Alveo U200 design 2021-10-19 17:45:43 -07:00
Alex Forencich
38e3244caa Rework GT instances in ExaNIC X10 design 2021-10-18 00:34:06 -07:00
Alex Forencich
fa77fe54f3 Rework GT instances in ExaNIC X25 design 2021-10-18 00:32:37 -07:00
Alex Forencich
4aa672f8f3 Update example designs 2021-10-17 20:20:26 -07:00
Alex Forencich
625c48c59c Add transceiver reset watchdog 2021-10-17 20:19:04 -07:00
Alex Forencich
7594ac0775 Init and reset to same value 2021-10-17 02:13:14 -07:00
Alex Forencich
45ddd70036 merged changes in axis 2021-10-17 01:42:17 -07:00
Alex Forencich
2cd70281ea Properly zero synchronized pointer on one-sided reset 2021-10-17 01:23:02 -07:00
Alex Forencich
9d4d8508ae Unconditionally pass through ordered set data to simplify decode logic 2021-10-16 01:25:48 -07:00
Alex Forencich
247aeae845 Detect bad XGMII encodings in PHY TX 2021-10-16 00:50:48 -07:00
Alex Forencich
3b2e6874d8 Rework XGMII to BASE-R encoder implementation 2021-10-16 00:48:01 -07:00
Alex Forencich
9667ef1f9c Detect sequence errors 2021-10-16 00:03:35 -07:00
Alex Forencich
5258bdc312 Improve bad block detection 2021-10-15 23:58:35 -07:00
Alex Forencich
571394f99f Translate LPI control characters 2021-10-15 23:53:53 -07:00
Alex Forencich
5494f3b678 Rewrite resets 2021-10-15 23:33:35 -07:00
Alex Forencich
a540e50e1c Fix XGMII to BASE-R control character mapping 2021-10-15 16:14:02 -07:00
Alex Forencich
a539a76ec4 Add cocotb testbenches for 10G MAC+PHY modules 2021-10-15 01:37:10 -07:00
Alex Forencich
e7dddc0dfd Add cocotb testbenches for AXI stream BASE-R TX and RX modules 2021-10-15 01:08:14 -07:00
Alex Forencich
8b95b33bab Add cocotb testbench for 10G PHY 2021-10-15 01:07:26 -07:00
Alex Forencich
2d9f01f9fe Add cocotb testbenches for XGMII BASE-R encoder and decoder modules 2021-10-15 01:06:57 -07:00
Alex Forencich
c0e2eb2b07 Add BASE-R serdes models for cocotb 2021-10-15 00:36:56 -07:00
Alex Forencich
70cb88629b merged changes in axis 2021-10-13 18:17:45 -07:00
Alex Forencich
10e24cc5b1 Fix timing constraints 2021-10-13 18:07:45 -07:00
Alex Forencich
4c14289fb0 Fix instance name 2021-10-13 14:43:42 -07:00
Alex Forencich
e85deafca3 Update FIFO instance 2021-10-13 14:42:57 -07:00
Alex Forencich
1d187b9b87 merged changes in axis 2021-10-13 14:12:11 -07:00
Alex Forencich
4f1eabab17 Split async FIFO resets 2021-10-13 14:05:13 -07:00
Alex Forencich
e0da1819c4 More tests for pipeline FIFO 2021-09-28 01:18:17 -07:00
Alex Forencich
0b5fc5b0e0 Fix off by one error 2021-09-28 01:17:57 -07:00
Alex Forencich
e48901a588 Reorganize test lists 2021-09-28 01:17:28 -07:00
Alex Forencich
d549267e17 Test async FIFO with different clock periods 2021-09-28 00:29:54 -07:00
Alex Forencich
e8c28e00cd Update tox configuration 2021-09-13 13:02:17 -07:00
Alex Forencich
c44e447db5 Transfer PTP information in tuser 2021-09-01 15:56:00 -07:00
Alex Forencich
b6f792cc10 merged changes in axis 2021-09-01 15:54:12 -07:00
Alex Forencich
6c234260b2 Fix assignment type 2021-09-01 15:53:15 -07:00
Alex Forencich
3db970636c merged changes in axis 2021-08-27 15:28:53 -07:00
Alex Forencich
6bcd96fa83 Bypass pipeline FIFO when length is zero 2021-08-27 13:54:14 -07:00
Alex Forencich
e7de9b6ee6 Update PTP CDC instances 2021-08-26 01:07:56 -07:00
Alex Forencich
77938fa422 Update MAC modules for changes in FIFO modules 2021-08-26 00:55:12 -07:00
Alex Forencich
5273a8dda6 merged changes in axis 2021-08-26 00:14:22 -07:00
Alex Forencich
a613cc8a31 Fix alignment 2021-08-25 23:58:52 -07:00
Alex Forencich
6d70b0249e Update readme 2021-08-25 23:58:33 -07:00
Alex Forencich
6a030f5d5e Add axis_pipeline_fifo 2021-08-25 23:54:30 -07:00
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
Alex Forencich
0b2066abe3 Fix corner case with back-to-back single-cycle transfers 2021-08-25 19:19:30 -07:00