263 Commits

Author	SHA1	Message	Date
Alex Forencich	e548bd0238	Initialize RAMs	2019-08-20 01:06:29 -07:00
Alex Forencich	d977cbdac2	Add feature bits	2019-08-19 23:43:52 -07:00
Alex Forencich	5f066b9fcd	Adjust ExaNIC board ID to match original PCIe ID	2019-08-19 22:04:10 -07:00
Alex Forencich	0fd9bc7376	merged changes in pcie	2019-08-19 14:32:55 -07:00
Alex Forencich	c9a17cdf90	Init scheduler queue state on reset	2019-08-13 13:51:50 -07:00
Alex Forencich	94c8dabad6	Rewrite scheduler	2019-08-13 00:45:01 -07:00
Alex Forencich	aeaabfeff5	Truncate high order address bits	2019-08-13 00:41:10 -07:00
Alex Forencich	80f06e1fcc	Update testbenches	2019-08-13 00:39:28 -07:00
Alex Forencich	d99f40db08	Add port CSRs	2019-08-13 00:27:09 -07:00
Alex Forencich	451acd3af5	Parametrize queue RAM width	2019-08-11 15:15:55 -07:00
Alex Forencich	1e06d7cca7	Clean up pipeline parameters	2019-08-11 09:55:10 -07:00
Alex Forencich	46fe4bbd97	Remove extraneous code	2019-08-11 00:34:50 -07:00
Alex Forencich	f6244afdd2	Add symlink	2019-08-11 00:33:22 -07:00
Alex Forencich	afbec29b52	merged changes in pcie	2019-08-04 00:39:35 -07:00
Alex Forencich	13835c18a1	merged changes in pcie	2019-08-03 23:33:15 -07:00
Alex Forencich	f1024f72cb	merged changes in eth	2019-07-29 18:56:36 -07:00
Alex Forencich	2fbbfb05f9	Parametrize channel assignments	2019-07-28 16:02:54 -07:00
Alex Forencich	0709e4e09f	Remove extraneous parameter	2019-07-28 16:01:05 -07:00
Alex Forencich	26f6774182	Parameter updates and documentation	2019-07-27 23:47:46 -07:00
Alex Forencich	772e01c95c	Add VCU118 mqnic_tdma design	2019-07-25 20:24:32 -07:00
Alex Forencich	089a46c811	Add VCU118 mqnic design	2019-07-25 20:21:11 -07:00
Alex Forencich	5b8898f2bc	Add VCU108 mqnic_tdma design	2019-07-25 17:44:13 -07:00
Alex Forencich	958aec8e8c	Add VCU108 mqnic design	2019-07-25 17:05:56 -07:00
Alex Forencich	90900f144a	merged changes in axi	2019-07-24 18:19:15 -07:00
Alex Forencich	e809912456	merged changes in eth	2019-07-24 18:02:17 -07:00
Alex Forencich	db297ce725	merged changes in pcie	2019-07-24 18:02:14 -07:00
Alex Forencich	574aeeef63	merged changes in axi	2019-07-24 18:02:10 -07:00
Alex Forencich	0a16bb1299	Fix parametrization	2019-07-24 01:45:18 -07:00
Alex Forencich	a6c4b8b1b7	Change board IDs	2019-07-21 15:27:01 -07:00
Alex Forencich	ea7ccd182e	Move MAC out of port module	2019-07-19 23:29:03 -07:00
Alex Forencich	1917ed3912	merged changes in eth	2019-07-19 18:17:57 -07:00
Alex Forencich	9de2101cdc	Update ExaNIC X10 testbenches	2019-07-19 18:01:24 -07:00
Alex Forencich	eb92578699	Update FIFO instances	2019-07-19 16:17:36 -07:00
Alex Forencich	00ebe73bdc	merged changes in eth	2019-07-19 15:52:41 -07:00
Alex Forencich	5b15f03f69	Add ADM-PCIE-9V3 mqnic_tdma design	2019-07-19 15:43:40 -07:00
Alex Forencich	a9179dc550	Add ExaNIC X10 mqnic_tdma design	2019-07-19 15:42:18 -07:00
Alex Forencich	4b37a4484d	Add TDMA round-robin scheduler	2019-07-19 15:40:53 -07:00
Alex Forencich	750112ff06	Add ADM-PCIE-9V3 mqnic design	2019-07-19 15:39:40 -07:00
Alex Forencich	4c3f2412df	Add TDMA BERT modules and testbenches	2019-07-19 15:28:57 -07:00
Alex Forencich	1df012a8d4	Add ExaNIC X10 design	2019-07-17 16:57:04 -07:00
Alex Forencich	fcd8b1b8e9	Add driver simulation model	2019-07-17 16:46:12 -07:00
Alex Forencich	ce011453d6	Add interface module	2019-07-17 16:43:12 -07:00
Alex Forencich	351404813a	Add port module	2019-07-17 16:42:39 -07:00
Alex Forencich	65f0ff28b5	Add Ethernet interface module	2019-07-17 16:41:21 -07:00
Alex Forencich	12f215fe26	Add round robin transmit scheduler	2019-07-17 16:40:35 -07:00
Alex Forencich	bda4e87371	Add event management modules	2019-07-17 16:39:59 -07:00
Alex Forencich	f94e83e520	Add transmit and receive engines	2019-07-17 16:38:57 -07:00
Alex Forencich	6100e3ad78	Add RX checksum module and testbench	2019-07-16 00:42:49 -07:00
Alex Forencich	755c7959be	merged changes in eth	2019-07-16 00:40:02 -07:00
Alex Forencich	a653f2d839	Add TDMA scheduler module and testbench	2019-07-16 00:19:22 -07:00