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Author SHA1 Message Date
Alex Forencich
a1d0fb810f Reorganize 2019-12-02 15:27:27 -08:00
Alex Forencich
2afef8c6d8 Fix use before define 2019-12-02 15:18:08 -08:00
Alex Forencich
80dafd5870 Check FIFO depth 2019-12-02 15:15:24 -08:00
Alex Forencich
2dbe6e19ab Reset mask FIFO pointers 2019-12-02 14:07:17 -08:00
Alex Forencich
a7be8e8f87 Clear the sequence number valid bits 2019-11-27 16:43:15 -08:00
Alex Forencich
546ef162dd Rewrite reset 2019-11-26 16:44:46 -08:00
Alex Forencich
4c8fcef230 Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules 2019-11-26 16:30:30 -08:00
Alex Forencich
c5a0d05b47 Add OP_TABLE_SIZE parameter to testbenches 2019-11-26 00:00:49 -08:00
Alex Forencich
e7bd0a62f1 Implement RQ sequence numbers in Ultrascale models 2019-11-25 18:07:49 -08:00
Alex Forencich
bbcdcc17bc Rename OP_TAG_WIDTH to OP_TABLE_SIZE 2019-11-25 14:59:53 -08:00
Alex Forencich
82030d3720 Use correct RAM size for initialization 2019-11-24 15:38:10 -08:00
Alex Forencich
176e1159a3 Update python parameter computation to match verilog clog2 2019-11-24 00:01:33 -08:00
Alex Forencich
f6f8e556ef Update tag parameters 2019-11-23 21:18:46 -08:00
Alex Forencich
6c6e3c8212 Remove extraneous parameter connections 2019-11-23 21:15:33 -08:00
Alex Forencich
b2c5004962 Fix discontinue masks 2019-11-23 00:20:21 -08:00
Alex Forencich
f35d576301 Add mqnic-dump utility 2019-11-21 17:08:40 -08:00
Alex Forencich
317aa34db5 Expose control bits 2019-11-21 15:12:49 -08:00
Alex Forencich
e696433ecc Support changing MTU 2019-11-19 13:30:35 -08:00
Alex Forencich
2647f68124 Reset pointers after clearing buffers 2019-11-19 13:12:47 -08:00
Alex Forencich
463f2053b0 Add port register port_mtu 2019-11-18 16:30:32 -08:00
Alex Forencich
03465b4b25 Fix parameter 2019-11-18 16:27:02 -08:00
Alex Forencich
af434c8eba Add state_lock 2019-11-18 16:17:27 -08:00
Alex Forencich
a77effe885 Remove quotes 2019-11-17 12:51:13 -08:00
Alex Forencich
489506e4c0 Add FPGA ID register 2019-11-17 12:46:27 -08:00
Alex Forencich
445f80e6f2 Connect QSPI flash on Alpha Data board 2019-11-17 01:01:52 -08:00
Alex Forencich
ee532a2472 Check tag count based on target device 2019-11-15 14:57:23 -08:00
Alex Forencich
52c502227f Remove unused client tag ports and parameters 2019-11-15 00:55:13 -08:00
Alex Forencich
33be402b16 Update widths 2019-11-14 00:02:10 -08:00
Alex Forencich
bce2756c0c Parametrize checksum offload 2019-11-13 23:49:50 -08:00
Alex Forencich
334738a567 Set misc device parent to aid in device discovery 2019-11-10 14:44:20 -08:00
Alex Forencich
eddd7c3b03 Update makefile 2019-11-06 16:45:44 -08:00
Alex Forencich
f36773660d Set flash ID 2019-11-06 15:05:32 -08:00
Alex Forencich
8dd5d02e35 Add tx_queue_count field to mqnic_port, remove unnecessary arguments 2019-11-06 11:40:27 -08:00
Alex Forencich
ed7e374afa Remove obsolete driver code 2019-11-06 11:32:33 -08:00
Alex Forencich
0dc24a7baa Update readme 2019-11-05 22:13:26 -08:00
Alex Forencich
c954b55da9 Remove tx_scheduler_tdma_rr module 2019-11-05 22:10:47 -08:00
Alex Forencich
3655a6df00 Use new TDMA scheduler control module 2019-11-05 22:09:51 -08:00
Alex Forencich
93de8a1b32 Remove extraneous init code 2019-11-05 18:32:36 -08:00
Alex Forencich
e43c011e33 Update testbenches 2019-11-05 18:31:41 -08:00
Alex Forencich
7fb022abe1 Add tx_scheduler_ctrl_tdma module 2019-11-05 18:24:22 -08:00
Alex Forencich
29d223f0ab Add mqnic_sched struct 2019-11-05 18:21:08 -08:00
Alex Forencich
abdb714fd9 Read timeslot count 2019-11-05 18:20:21 -08:00
Alex Forencich
f53a6b20e8 Add timeslot count to port registers 2019-11-05 16:59:40 -08:00
Alex Forencich
f65b139797 Add scheduler control input to tx_scheduler_rr 2019-11-05 16:56:10 -08:00
Alex Forencich
304e0b7410 Update TDMA scheduler to generate status signals and avoid producing runt outputs 2019-11-05 16:55:19 -08:00
Alex Forencich
21e505386a Update mqnic-config 2019-11-05 16:51:28 -08:00
Alex Forencich
fa5e013255 Add MQNIC_MAX_SCHED define 2019-11-05 16:45:58 -08:00
Alex Forencich
e92485a41e Fix register definitions 2019-11-05 16:44:57 -08:00
Alex Forencich
cc592b44d7 Use correct PCIe core model 2019-11-04 14:13:12 -08:00
Alex Forencich
34c97150e8 Fix get_free_tag 2019-11-04 14:11:24 -08:00