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Author SHA1 Message Date
Alex Forencich
097244162e Add VCU108 example design 2019-11-01 18:19:23 -07:00
Alex Forencich
cf45a1b6fa Update port handling 2019-11-01 16:34:14 -07:00
Alex Forencich
381fd871c5 Parametrize tag widths 2019-10-31 23:25:34 -07:00
Alex Forencich
736321641f Parametrize addressing 2019-10-31 23:24:42 -07:00
Alex Forencich
d97407f245 merged changes in axi 2019-10-31 14:46:25 -07:00
Alex Forencich
7c69ab9e49 Add default addressing capability to interconnect modules 2019-10-31 14:44:26 -07:00
Alex Forencich
7583ce3ea3 Print addressing configuration 2019-10-30 23:22:45 -07:00
Alex Forencich
ed6f5b3655 Update overlap error message 2019-10-30 23:21:29 -07:00
Alex Forencich
4e95fb3677 Bypass check when unneeded 2019-10-30 22:57:56 -07:00
Alex Forencich
25454e712e Remove constant regs 2019-10-30 22:56:27 -07:00
Alex Forencich
f43cd09dac Add ExaNIC X25 mqnic design 2019-10-30 17:43:33 -07:00
Alex Forencich
b34f294900 Add ExaNIC X25 10G example design 2019-10-30 17:14:27 -07:00
Alex Forencich
4fcea4e875 Add ExaNIC X25 example design 2019-10-30 17:13:25 -07:00
Alex Forencich
c9193109d1 Rename example designs 2019-10-30 16:48:58 -07:00
Alex Forencich
533f19dfb7 merged changes in eth 2019-10-24 12:13:08 -07:00
Alex Forencich
9ef08c9d5d merged changes in axis 2019-10-24 12:09:16 -07:00
Alex Forencich
a9c04a4651 Fix frame FIFO drop 2019-10-24 12:08:08 -07:00
Alex Forencich
b3c654461e Update example design 2019-10-22 23:17:39 -07:00
Alex Forencich
407c2a3a62 merged changes in pcie 2019-10-22 16:07:47 -07:00
Alex Forencich
c43a3eb41a Fix latch inference 2019-10-22 16:03:58 -07:00
Alex Forencich
458a7fc598 Prioritize read request passthrough 2019-10-20 23:30:16 -07:00
Alex Forencich
771c3af93f Remove debug code 2019-10-20 23:21:21 -07:00
Alex Forencich
a65067d515 Update readme 2019-10-19 00:47:00 -07:00
Alex Forencich
415c2b36be Remove old code 2019-10-19 00:38:52 -07:00
Alex Forencich
6473786a4c Add 25G mqnic design for Alpha Data board 2019-10-18 03:26:46 -07:00
Alex Forencich
f2694d8ba3 Update readme 2019-10-17 19:50:49 -07:00
Alex Forencich
02cc2c7377 Use PCIe gen 3 x16 2019-10-17 19:02:46 -07:00
Alex Forencich
1a06f16130 Update VCU118 XDC file 2019-10-17 16:07:42 -07:00
Alex Forencich
8fa7e40507 Use new DMA subsystem 2019-10-17 16:02:14 -07:00
Alex Forencich
16c5eee499 merged changes in pcie 2019-10-17 11:46:24 -07:00
Alex Forencich
edfb962bf5 Byte enable computation optimizations 2019-10-17 11:41:56 -07:00
Alex Forencich
19ae70dcaa Fix bad optimization 2019-10-16 00:30:10 -07:00
Alex Forencich
b0c97e8d23 Add missing parameter connection 2019-10-14 23:52:38 -07:00
Alex Forencich
3a791afd37 Update DMA interface modules to support 512 bit interface 2019-10-14 16:23:18 -07:00
Alex Forencich
553d7e05fe Update AXI DMA modules to support 512 bit interface 2019-10-14 16:22:09 -07:00
Alex Forencich
f8bc6c31e5 Update AXI master modules to support 512 bit interface 2019-10-14 16:20:46 -07:00
Alex Forencich
128c9ca015 Update demux modules to support 512 bit interface 2019-10-14 16:01:38 -07:00
Alex Forencich
af09059248 Update AXI lite master module to support 512 bit interface 2019-10-14 15:58:38 -07:00
Alex Forencich
39200d84cb Update simulation models to support 512 bit interface 2019-10-14 15:45:41 -07:00
Alex Forencich
89ff925545 Timing optimizations 2019-10-14 14:00:55 -07:00
Alex Forencich
e96ee85356 Update example designs 2019-10-13 17:16:01 -07:00
Alex Forencich
2c43a6e189 Use mmap objects instead of bytearrays 2019-10-13 15:41:12 -07:00
Alex Forencich
75563c65f0 Add DMA interface mux modules 2019-10-12 23:08:21 -07:00
Alex Forencich
fdd7faef4f Add Xilinx Ultrascale PCIe DMA interface modules and testbenches 2019-10-12 23:03:42 -07:00
Alex Forencich
25de311347 Add DMA RAM module 2019-10-12 22:48:23 -07:00
Alex Forencich
e1035ed57d Add AXI stream sink DMA client module and testbench 2019-10-12 22:35:57 -07:00
Alex Forencich
baeeb8ea5c Add AXI stream source DMA client module and testbench 2019-10-12 22:34:15 -07:00
Alex Forencich
5e9254d519 Check is_eof_0 in RCSink 2019-10-12 18:58:27 -07:00
Alex Forencich
9b5a5db4d1 Add USPcieFrame intermediate format 2019-10-12 18:01:39 -07:00
Alex Forencich
603a6e18e2 Fix RC channel sideband byte enables 2019-10-11 14:16:44 -07:00