FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity
1,382 Commits 1 Branch 0 Tags
Commit Graph

21 Commits

Author SHA1 Message Date
Alex Forencich
ca0cbf4d93 Update parameters 2020-05-01 17:22:21 -07:00
Alex Forencich
e14cfa0a58 Update port and interface modules 2020-04-20 21:25:21 -07:00
Alex Forencich
50af74aa88 Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH 2020-04-20 18:43:26 -07:00
Alex Forencich
627153cd9b Fix signal sizing bug 2020-03-06 00:24:13 -08:00
Alex Forencich
3690fdeb7d Pull out pipeline parameters 2019-12-28 01:16:16 -08:00
Alex Forencich
7a68abbb84 Split control and data descriptor paths to DMA engine 2019-12-13 14:15:25 -08:00
Alex Forencich
6270278c75 Add RSS support 2019-12-06 14:15:16 -08:00
Alex Forencich
381fd871c5 Parametrize tag widths 2019-10-31 23:25:34 -07:00
Alex Forencich
736321641f Parametrize addressing 2019-10-31 23:24:42 -07:00
Alex Forencich
8fa7e40507 Use new DMA subsystem 2019-10-17 16:02:14 -07:00
Alex Forencich
2325966973 Pull out descriptor and completion handling logic 2019-09-23 18:10:35 -07:00
Alex Forencich
132d44cd90 Increase crossbar threads count 2019-09-11 18:06:14 -07:00
Alex Forencich
bcfd665823 Connect queue index field in queue operation response 2019-09-01 08:29:22 -07:00
Alex Forencich
d67c9ff70e Pull out scheduler op table size parameter 2019-08-23 07:44:33 -07:00
Alex Forencich
d977cbdac2 Add feature bits 2019-08-19 23:43:52 -07:00
Alex Forencich
1e06d7cca7 Clean up pipeline parameters 2019-08-11 09:55:10 -07:00
Alex Forencich
0709e4e09f Remove extraneous parameter 2019-07-28 16:01:05 -07:00
Alex Forencich
26f6774182 Parameter updates and documentation 2019-07-27 23:47:46 -07:00
Alex Forencich
ea7ccd182e Move MAC out of port module 2019-07-19 23:29:03 -07:00
Alex Forencich
eb92578699 Update FIFO instances 2019-07-19 16:17:36 -07:00
Alex Forencich
ce011453d6 Add interface module 2019-07-17 16:43:12 -07:00