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300 Commits 1 Branch 0 Tags
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133 Commits

Author SHA1 Message Date
Alex Forencich
e48901a588 Reorganize test lists 2021-09-28 01:17:28 -07:00
Alex Forencich
d549267e17 Test async FIFO with different clock periods 2021-09-28 00:29:54 -07:00
Alex Forencich
6bcd96fa83 Bypass pipeline FIFO when length is zero 2021-08-27 13:54:14 -07:00
Alex Forencich
6a030f5d5e Add axis_pipeline_fifo 2021-08-25 23:54:30 -07:00
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
sungsoo.han
edaec3bd38 add LAST_ENABLE to axis_arb_mux 2021-08-17 16:00:23 +09:00
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
5d9c982cd4 Add switch testbenches 2021-05-30 12:33:29 -07:00
Alex Forencich
9417d5f749 Use cocotb.top 2021-05-30 12:32:02 -07:00
Alex Forencich
c1bfa8cc41 Add tuser assert tests 2021-05-25 00:55:59 -07:00
Alex Forencich
a7905ed681 Add stress tests 2021-05-25 00:31:20 -07:00
Alex Forencich
a7ebfdcebb Add arbitration test 2021-05-25 00:13:32 -07:00
Alex Forencich
74c1014671 Add cocotb testbenches 2021-04-03 16:53:08 -07:00
Alex Forencich
ede73b434a Add PIPELINE_OUTPUT parameter to FIFO adapter modules 2020-09-07 00:22:55 -07:00
Alex Forencich
2f883681d6 Add pararametrizable output pipeline to FIFOs 2020-09-07 00:14:22 -07:00
Alex Forencich
a7689b6772 Pipeline RAM output in RAM switch 2020-09-03 15:55:45 -07:00
Alex Forencich
52d1117753 Add AXI stream RAM switch module and testbenches 2020-02-18 01:06:14 -08:00
Alex Forencich
8179a32b7d Pass all parameters in testbenches 2019-07-24 15:26:49 -07:00
Alex Forencich
69de6fd2a4 Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH 2019-07-18 11:27:25 -07:00
Alex Forencich
1d5a4db0d5 Unconditionally wait at least one delta cycle 2019-07-16 00:30:19 -07:00
Alex Forencich
8e969aa14c Add FIFO/width adapter wrapper modules 2019-04-26 18:38:25 -07:00
Alex Forencich
e3fcb0fa1d Test shorter frames 2019-04-26 18:36:09 -07:00
Alex Forencich
a9c7946368 Change parameter concatenation to increments of DEST_WIDTH 2019-03-28 23:49:04 -07:00
Alex Forencich
3920b2801e Add short packet tests 2019-03-26 16:39:31 -07:00
Alex Forencich
d2df971fc9 Add AXI stream frame length measurement module and testbenches 2019-03-07 22:57:46 -08:00
Alex Forencich
e0f740457b Testbench updates 2019-03-07 22:51:40 -08:00
Alex Forencich
b60886a0ec Add AXI stream broadcast module and testbench 2019-02-27 19:46:30 -08:00
Alex Forencich
59a979aeda Add parameters to testbench 2018-12-09 00:05:38 -08:00
Alex Forencich
f9a5e6803b Add backpressure tests 2018-12-08 23:59:57 -08:00
Alex Forencich
ded363b471 Rename status outputs 2018-10-25 15:36:34 -07:00
Alex Forencich
e9d9f32150 Rename ports 2018-10-25 12:00:34 -07:00
Alex Forencich
6f4ab8f180 Rename ports 2018-10-25 11:59:13 -07:00
Alex Forencich
84a758f100 Rename ports 2018-10-25 11:56:52 -07:00
Alex Forencich
6c1ea89a66 Rename ports 2018-10-25 11:52:08 -07:00
Alex Forencich
fd28040c40 Rename ports 2018-10-25 11:30:35 -07:00
Alex Forencich
7997a4a844 Rename ports 2018-10-25 11:19:28 -07:00
Alex Forencich
cb9f2132a4 Update parameter ordering 2018-10-25 10:20:17 -07:00
Alex Forencich
09a8fa51b6 Rename ports 2018-10-25 10:19:32 -07:00
Alex Forencich
c47f3ea03d Update FIFO instance, rename ports 2018-10-25 10:17:58 -07:00
Alex Forencich
d1ed1528b5 Update FIFO instance, rename ports 2018-10-25 10:15:16 -07:00
Alex Forencich
11d9dbe24a Merge axis_async_fifo and axis_async_frame_fifo, rename ports 2018-10-25 09:53:38 -07:00
Alex Forencich
36d0a8786f Merge axis_fifo and axis_frame_fifo, rename ports 2018-10-24 23:16:06 -07:00
Alex Forencich
3bbf8524d6 Compute DEST_WIDTH 2018-10-24 22:21:31 -07:00
Alex Forencich
9d813226d0 Convert generated demux to verilog parametrized demux 2018-10-24 22:16:05 -07:00
Alex Forencich
2bf15706cd Convert generated mux to verilog parametrized mux 2018-10-24 18:23:14 -07:00
Alex Forencich
fc6c07e5f9 Convert generated frame joiner to verilog parametrized frame joiner 2018-10-24 17:07:22 -07:00
Alex Forencich
fd7f65d5ad Convert generated switch to verilog parametrized switch 2018-10-24 16:12:56 -07:00
Alex Forencich
631147069f Rename ports and add reg_type parameter to axis_register 2018-10-24 14:35:08 -07:00
Alex Forencich
940c1210c1 Convert arbitrated mux to verilog parametrized arbitrated mux 2018-10-24 13:49:17 -07:00
Alex Forencich
fe77db822d Convert generated crosspoint to verilog parametrized crosspoint 2018-10-24 13:44:39 -07:00