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6 Commits

Author SHA1 Message Date
Alex Forencich
e548bd0238 Initialize RAMs 2019-08-20 01:06:29 -07:00
Alex Forencich
451acd3af5 Parametrize queue RAM width 2019-08-11 15:15:55 -07:00
Alex Forencich
1e06d7cca7 Clean up pipeline parameters 2019-08-11 09:55:10 -07:00
Alex Forencich
46fe4bbd97 Remove extraneous code 2019-08-11 00:34:50 -07:00
Alex Forencich
26f6774182 Parameter updates and documentation 2019-07-27 23:47:46 -07:00
Alex Forencich
46f653f097 Add queue manager module and testbench 2019-07-16 00:15:50 -07:00