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142 Commits 1 Branch 0 Tags
Commit Graph

17 Commits

Author SHA1 Message Date
Alex Forencich
cd06f0b7dc Drop entire write operation on address decode fail in axi_interconnect 2020-10-19 00:13:40 -07:00
Alex Forencich
7c69ab9e49 Add default addressing capability to interconnect modules 2019-10-31 14:44:26 -07:00
Alex Forencich
7583ce3ea3 Print addressing configuration 2019-10-30 23:22:45 -07:00
Alex Forencich
ed6f5b3655 Update overlap error message 2019-10-30 23:21:29 -07:00
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62cbaa1bd1 Remove extraneous code 2019-07-25 15:44:37 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
a60e1f726f Fix use before define 2019-03-18 14:02:10 -07:00
Alex Forencich
7d0f3ef7a1 Fix address range overlap check to support arbitrary address widths 2018-12-04 17:00:26 -08:00
Alex Forencich
61df54e62d Add M_REGIONS and M_SECURE parameters, add address range overlap check 2018-12-03 13:17:45 -08:00
Alex Forencich
7141a75ce8 Remove region inputs 2018-12-03 13:15:55 -08:00
Alex Forencich
b289e02fe4 Remove extraneous code 2018-08-26 14:06:57 -07:00
Alex Forencich
71427e7cf0 Update default parameters 2018-08-26 14:05:10 -07:00
Alex Forencich
07a4da3bea Fix connect logic 2018-08-23 16:20:58 -07:00
Alex Forencich
4f01dfb7d5 Support single slave interface 2018-08-23 14:43:57 -07:00
Alex Forencich
f1fb5b368c Fix connect logic 2018-08-23 14:41:40 -07:00
Alex Forencich
a25c4b17eb Add AXI shared interconnect and testbench 2018-08-22 23:42:31 -07:00