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Commit Graph

201 Commits

Author SHA1 Message Date
Alex Forencich
77b9cace47 Update BAR configuration in testbenches 2020-07-28 19:01:53 -07:00
Alex Forencich
ffd04d2bb0 Cleanup 2020-07-28 19:00:33 -07:00
Alex Forencich
495178e1dc Fix mask 2020-07-28 18:30:52 -07:00
Alex Forencich
e4566dc545 merged changes in pcie 2020-07-28 16:00:31 -07:00
Alex Forencich
d449be8fc5 Convert to 64 bit BARs 2020-07-24 16:54:57 -07:00
Alex Forencich
2a23be508a Add 100G mqnic design for Alveo U50 2020-07-17 01:44:59 -07:00
Alex Forencich
deb895ff05 Add 10G mqnic design for Alveo U50 2020-07-17 01:44:28 -07:00
Alex Forencich
18f56fcb16 Remove extraneous signals 2020-07-17 00:57:47 -07:00
Alex Forencich
837a390567 Fix VCU118 CMAC reference clocks 2020-07-14 10:47:18 -07:00
Alex Forencich
20eac98bde Clean up 2020-07-14 00:33:12 -07:00
Alex Forencich
e230fecb23 XDC clean up 2020-07-13 23:58:39 -07:00
Alex Forencich
9b7fa688d5 Add 100G mqnic design for Alveo U280 2020-07-12 11:33:28 -07:00
Alex Forencich
6433275139 Add 10G mqnic design for Alveo U280 2020-07-12 11:33:18 -07:00
Alex Forencich
f99736d4f5 Convert to TCL IP 2020-07-11 20:07:13 -07:00
Alex Forencich
5dd5f8bb3e merged changes in pcie 2020-07-10 19:46:48 -07:00
Alex Forencich
7c10036183 merged changes in eth 2020-07-10 19:46:43 -07:00
Alex Forencich
0ff6282ed6 merged changes in axi 2020-07-10 19:46:37 -07:00
Alex Forencich
4e958096b2 Update driver model to set MTU registers 2020-05-01 19:19:56 -07:00
Alex Forencich
ae775a9386 Rewrite RX buffer management 2020-05-01 19:00:58 -07:00
Alex Forencich
8b535e54ac Add MTU registers 2020-05-01 18:55:01 -07:00
Alex Forencich
ca0cbf4d93 Update parameters 2020-05-01 17:22:21 -07:00
Alex Forencich
1f76606667 Move TDMA registers 2020-05-01 16:55:57 -07:00
Alex Forencich
ded213460d Rewrite TX buffer management 2020-05-01 14:29:52 -07:00
Alex Forencich
1c7b7937e5 Limit in-flight descriptor requests in TX engine 2020-04-30 23:37:41 -07:00
Alex Forencich
45ec6657b1 Limit in-flight descriptor requests in RX engine 2020-04-30 23:29:43 -07:00
Alex Forencich
31cec8d0c1 Fix cmac_pad frame truncation bug 2020-04-22 23:23:34 -07:00
Alex Forencich
9e64d19ea5 Use scatter descriptor blocks in driver model 2020-04-21 01:04:07 -07:00
Alex Forencich
2c6e9673f7 Add log_desc_block_size ring parameter in driver model 2020-04-21 00:58:12 -07:00
Alex Forencich
e14cfa0a58 Update port and interface modules 2020-04-20 21:25:21 -07:00
Alex Forencich
7087a595e9 Update RX and TX engines to support descriptor blocks 2020-04-20 21:24:25 -07:00
Alex Forencich
0fb60d718d Add log desc block size to desc_fetch module 2020-04-20 21:01:55 -07:00
Alex Forencich
d0cf549057 Add log desc block size field to queue manager 2020-04-20 20:45:10 -07:00
Alex Forencich
50af74aa88 Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH 2020-04-20 18:43:26 -07:00
Alex Forencich
105a834790 Add mqnic design for NetFPGA SUME 2020-03-28 00:44:04 -07:00
Alex Forencich
9e3e80661c Use common sync_reset module 2020-03-27 23:53:05 -07:00
Alex Forencich
c364bab778 merged changes in eth 2020-03-27 19:08:47 -07:00
Alex Forencich
3786cf0ca3 merged changes in pcie 2020-03-26 17:25:23 -07:00
Alex Forencich
ec03a36f98 Add 100G mqnic design for VCU118 2020-03-25 23:02:36 -07:00
Alex Forencich
309ee212bc merged changes in pcie 2020-03-24 23:25:56 -07:00
Alex Forencich
a196cd227c Enable bus mastering and MSI in driver model 2020-03-12 15:32:08 -07:00
Alex Forencich
457f4d7f3f Use configured ring stride 2020-03-12 15:28:00 -07:00
Alex Forencich
0c32192226 Use constants instead of magic numbers 2020-03-12 15:08:20 -07:00
Alex Forencich
1216f7a76e Offset packet start by 10 bytes to match Linux kernel skb alignment 2020-03-08 21:56:08 -07:00
Alex Forencich
23aef37aff Rewrite resets 2020-03-08 16:56:06 -07:00
Alex Forencich
24eae58e6c merged changes in pcie 2020-03-08 15:25:28 -07:00
Alex Forencich
248a0b4f93 Convert descriptor to DMA operation without storing in table 2020-03-08 00:22:55 -08:00
Alex Forencich
f7a1a7ef95 Add descriptor FIFOs 2020-03-07 22:28:59 -08:00
Alex Forencich
4dd5104f4d Stripe completion queues across event queues 2020-03-06 00:58:30 -08:00
Alex Forencich
627153cd9b Fix signal sizing bug 2020-03-06 00:24:13 -08:00
Alex Forencich
2b14ab2555 Update cmac_pad to pad frames to 60 bytes 2020-02-26 13:36:19 -08:00