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2,822 Commits 1 Branch 0 Tags
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134 Commits

Author SHA1 Message Date
Alex Forencich
5f9e33e8ab fpga/mqnic: Enable overtemp shutdown on all boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 15:23:23 -08:00
Alex Forencich
e8aaadd102 fpga: Clean up top-level PCIe interface parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 23:56:56 -08:00
Alex Forencich
08f49d7e17 fpga/mqnic: Add missing DRP frequency parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 22:07:58 -08:00
Alex Forencich
0644a12a48 fpga/mqnic: Remove extraneous top-level parameter RX_RSS_ENABLE from config.tcl scripts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 21:32:51 -08:00
Alex Forencich
347a03b347 fpga/mqnic: Rework PCIe IP core configuration, fixes disrupted MSI-X settings with application section enabled and issues with PCIe class code on 7-series and UltraScale 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 18:16:12 -08:00
Alex Forencich
c5003d0c6d fpga/mqnic: Select advanced mode for Xilinx PCIe IP core config to access MSI-X settings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 15:35:16 -08:00
Alex Forencich
2eafa56c75 fpga/mqnic/AU200: Add DMA bench target for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-01 17:51:16 -08:00
Alex Forencich
f67bd98719 Use CMAC wrapper in 100G mqnic design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 12:38:14 -08:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
01df80df86 fpga/mqnic: Disable MIGs by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 23:57:27 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 19:00:49 -07:00
Alex Forencich
eb990643f2 fpga/mqnic: various minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:07 -07:00
Alex Forencich
5f1e74b0e1 Add PROJECT variable, remove multiple stem matches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 13:33:09 -07:00
Alex Forencich
7017e7d49b Explicitly set top module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:29:01 -07:00
Alex Forencich
ceb6a9ca06 Update clean target 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:26:39 -07:00
Alex Forencich
9c98f12392 Write debug probes file alongside bit file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 23:37:54 -07:00
Alex Forencich
9628401780 Normalize output file location 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 21:47:53 -07:00
Alex Forencich
caf2a0993b fpga: Output hierarchical utilization reports 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-06 21:17:25 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
81648cf85b fpga/mqnic: Clean up PCIe DMA IF flow control connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:05 -07:00
Alex Forencich
218f2e2bb3 25G designs use double width sync datapath by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 23:31:36 -07:00
Alex Forencich
c76e152804 Rename cmac_ts_insert to mac_ts_insert 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:27:27 -07:00
Alex Forencich
ef5b2449dc Add stretched PTP PPS output 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:58 -07:00
Alex Forencich
676f3edd2d Add TX PTP clock to port map module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:39 -07:00
Alex Forencich
e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:41 -07:00
Alex Forencich
33b798540e Change hex format in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:20:48 -07:00
Alex Forencich
729c3a0458 Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-08 22:07:18 -07:00
Alex Forencich
a5d7833bd9 Update testbenches for new version of cocotbext-pcie 2022-06-05 00:24:42 -07:00
Alex Forencich
21b0f014a5 Switch to MSI-X 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:58:29 -07:00
Alex Forencich
dd2853bf40 Update testbenches for latest version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-30 13:10:39 -07:00
Alex Forencich
5da044826d Add board-level configuration parameter for TDMA BER module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 11:25:58 -07:00
Alex Forencich
0c7bdb5635 Add missing QSFP28 control signal connections on AU200 and AU250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 01:30:19 -07:00
Alex Forencich
ed2d34153d Use PHY rx_status signal for link status detection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-17 00:46:05 -07:00
Alex Forencich
814a51a37c Use 128 KB RX RAM size for 25G designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 13:24:56 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
18d5c325bf Fix CMAC RX PTP timestamps 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 23:21:11 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
f67c704b11 Update placement constraints for hierarchy changes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-02 13:16:20 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00
Alex Forencich
53f3547ef5 Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-29 14:32:57 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
7f8bbe30de Add application ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:15:45 -07:00
Alex Forencich
ba70498518 fpga: Add DMA immediate connections and parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 15:00:58 -07:00
Alex Forencich
eb530475fb More expressive flash format register 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-15 18:38:01 -07:00
Alex Forencich
47f0044099 fpga/mqnic: Fix incorrect SLR in placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-14 11:51:10 -07:00
Alex Forencich
f58d922e8f fpga/mqnic: Use correct clock frequencies in 25G testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-13 20:20:01 -07:00
Alex Forencich
f687aba432 fpga/mqnic: Update designs to use port mapping modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-13 01:37:10 -07:00
Alex Forencich
c5d5fe8a64 fpga/mqnic: Remove unused wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:02:44 -07:00