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2,390 Commits 1 Branch 0 Tags
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6 Commits

Author SHA1 Message Date
Alex Forencich
e95c132045 Route PCIe user reset through BUFG 2022-03-25 01:26:29 -07:00
Alex Forencich
6f197c7cb4 Add PHY instances to Ethernet pblocks 2022-03-24 21:30:55 -07:00
Alex Forencich
056f78716a Add pipeline registers 2022-03-17 15:39:44 -07:00
Alex Forencich
0e15a7a16b Avoid critical warning from placement constraints when configured with a single interface 2022-03-17 15:39:13 -07:00
Alex Forencich
25421b8994 Update placement constraints 2022-03-15 15:28:43 -07:00
Alex Forencich
67bd69a8d7 Unified 10G/25G design for AU50 2022-03-14 21:36:30 -07:00