FPGA/corundum
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2,390 Commits 1 Branch 0 Tags
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3 Commits

Author SHA1 Message Date
Alex Forencich
e95c132045 Route PCIe user reset through BUFG 2022-03-25 01:26:29 -07:00
Alex Forencich
056f78716a Add pipeline registers 2022-03-17 15:39:44 -07:00
Alex Forencich
67bd69a8d7 Unified 10G/25G design for AU50 2022-03-14 21:36:30 -07:00