Alex Forencich
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6b256f82d3
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Generate pause frames on TX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-10 23:22:50 -07:00 |
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Alex Forencich
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448fa8eb4c
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Use SPDX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-26 11:44:57 -07:00 |
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Alex Forencich
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edc5903157
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fpga/common: Fix FIFO status connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-25 18:35:21 -07:00 |
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Alex Forencich
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f6262c3606
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fpga/mqnic: Update FIFO parameter naming
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-11-01 23:57:50 -07:00 |
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Alex Forencich
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36bd1f78b0
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Add missing parameter connection in rx_fifo
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2022-01-26 09:44:35 -08:00 |
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Alex Forencich
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335a5e890b
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Initial implementation of shared interface datapath
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2021-12-31 14:33:31 -08:00 |
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