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Author SHA1 Message Date
Alex Forencich
667b5c42c5 Add support for registering MSI callbacks 2019-01-28 16:30:19 -08:00
Alex Forencich
201c5faa80 Always ready on RC channel in idle for 64 bits 2019-01-22 23:00:17 -08:00
Alex Forencich
4422b908bf Backpressure for awvalid 2019-01-22 22:54:40 -08:00
Alex Forencich
fac972bfe6 RC channel backpressure fix 2019-01-22 22:50:15 -08:00
Alex Forencich
263bb5c670 Index based on correct tag value 2019-01-22 22:47:15 -08:00
Alex Forencich
a743f6f789 Add zero IFG forced offset start test 2019-01-22 18:47:32 -08:00
Alex Forencich
5b2d4fd465 Add force offset start parameter 2019-01-22 18:46:34 -08:00
Alex Forencich
4d2090a1a5 Fix off-by-one error in control character checks 2019-01-22 14:24:35 -08:00
Alex Forencich
92df3778ea Fix DIC implementation in testbench 2019-01-22 14:23:29 -08:00
Alex Forencich
9ae60dcd9a Simplify lane swapping code 2019-01-22 14:22:01 -08:00
Alex Forencich
54e31c51b7 Adjustment to scrambler bypass 2019-01-22 14:21:14 -08:00
Alex Forencich
6238ed5755 Report error for invalid encoding 2019-01-22 14:19:43 -08:00
Alex Forencich
e784900050 Remove unused code 2019-01-22 14:18:27 -08:00
Alex Forencich
a060d2eed9 Update readme 2019-01-18 16:22:24 -08:00
Alex Forencich
07b4efa9ba Switch out Xilinx PHY core in ExaNIC X10 example design 2019-01-18 13:49:46 -08:00
Alex Forencich
0bbe062c66 Switch out Xilinx PHY core in ADM-PCIE-9V3 example design 2019-01-18 13:32:58 -08:00
Alex Forencich
2e29aea857 Fix input clock period settings 2019-01-17 19:09:47 -08:00
Alex Forencich
787f198970 Add AXI lite dual-port RAM module and testbench 2019-01-17 17:48:23 -08:00
Alex Forencich
b1f40411ad Remove unnecessary reset 2019-01-17 17:09:55 -08:00
Alex Forencich
818fac5daa Update signal names 2019-01-16 19:37:15 -08:00
Alex Forencich
dbbbc28059 Add 10G Ethernet PHY modules and testbenches 2019-01-16 18:00:56 -08:00
Alex Forencich
91553e6edf Add XGMII 10GBASE-R encoder and decoder modules and testbenches 2019-01-16 17:30:07 -08:00
Alex Forencich
c9752f24dd Add BASE-R SERDES endpoint model 2019-01-16 17:26:19 -08:00
Alex Forencich
5fbd67501c Clamp ifg_cnt at zero 2019-01-16 17:25:08 -08:00
Alex Forencich
128dc292a1 Add short IFG tests 2019-01-16 13:27:28 -08:00
Alex Forencich
ea02b6c898 Properly handle short IFG 2019-01-16 13:26:47 -08:00
Alex Forencich
32d889b20d Remove unreachable code 2019-01-16 13:26:14 -08:00
Alex Forencich
bf94ef56b8 Move ifg parameter 2019-01-16 13:23:02 -08:00
Alex Forencich
b8b504682a Fix transceiver clocking 2019-01-15 00:30:36 -08:00
Alex Forencich
d86fb594c5 More fixes for tlp_cmd backpressure 2019-01-12 00:37:38 -08:00
Alex Forencich
5c24dcc1df Ensure tlp_cmd registers are clear when generating a new request 2019-01-11 01:27:52 -08:00
Alex Forencich
5cf9597201 Only generate a request if a tag is available 2019-01-10 19:00:19 -08:00
Alex Forencich
523bf689d8 Add optional output pipeline register to AXI lite RAM 2019-01-09 00:25:40 -08:00
Alex Forencich
6d52a7c0e7 Remove unneeded links 2019-01-08 17:31:49 -08:00
Alex Forencich
2628249059 Add ADM-PCIE-9V3 example design 2019-01-08 17:27:21 -08:00
Alex Forencich
1f793fa7d0 Update readme 2019-01-08 17:24:22 -08:00
Alex Forencich
82454e4ae1 Add ExaNIC X10 example design 2019-01-08 17:22:01 -08:00
Alex Forencich
73ece8451d Update readme 2019-01-07 21:40:54 -08:00
Alex Forencich
bb4fa0bfa0 Update testbenches 2019-01-02 02:00:46 -08:00
Alex Forencich
852d583282 Only store value when it is transferred 2019-01-02 01:59:29 -08:00
Alex Forencich
9b572ad0ac Fix bug 2019-01-02 01:59:05 -08:00
Alex Forencich
0a33ed17a7 Use correct parameter 2018-12-27 21:53:45 -08:00
Alex Forencich
c7958e1689 Add PCIe AXI DMA descriptor mux module 2018-12-27 19:02:15 -08:00
Alex Forencich
513a53e52d Add AXI DMA module and testbench 2018-12-27 14:21:06 -08:00
Alex Forencich
41f8667310 Add AXI write DMA module and testbenches 2018-12-27 14:15:51 -08:00
Alex Forencich
21ed77e4c0 Add AXI stream endpoint module 2018-12-27 13:49:48 -08:00
Alex Forencich
8b8cfd96fd merged changes in axis 2018-12-09 00:06:34 -08:00
Alex Forencich
59a979aeda Add parameters to testbench 2018-12-09 00:05:38 -08:00
Alex Forencich
8d9ed665d7 Use logical operator instead of bitwise 2018-12-09 00:04:56 -08:00
Alex Forencich
cadd1bcb50 Match width 2018-12-09 00:04:30 -08:00