Alex Forencich
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eb990643f2
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fpga/mqnic: various minor cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 17:12:07 -07:00 |
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Alex Forencich
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d7904b8007
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fpga: Add support for IRQ rate limiting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-04 15:24:40 -07:00 |
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Alex Forencich
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1486da601f
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fpga: Add clock period parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-04 12:03:35 -07:00 |
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Alex Forencich
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6c6648f114
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fpga/mqnic: Add RAM inference directive to Intel designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-05 16:27:29 -07:00 |
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Alex Forencich
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81648cf85b
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fpga/mqnic: Clean up PCIe DMA IF flow control connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 23:04:05 -07:00 |
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Alex Forencich
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3f57c2143b
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fpga/mqnic: PCIe interface updates
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 12:28:49 -07:00 |
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Alex Forencich
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607ce498cf
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fpga/mqnic: Update PCIe DMA settings on Intel designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 00:42:19 -07:00 |
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Alex Forencich
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6a29073aa6
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fpga/mqnic/S10MX_DK: Update S10MX dev kit design to support 25G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-25 21:25:21 -07:00 |
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