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Author SHA1 Message Date
Alex Forencich
ed2d34153d Use PHY rx_status signal for link status detection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-17 00:46:05 -07:00
Alex Forencich
5058b797d2 merged changes in eth 2022-05-16 23:23:27 -07:00
Alex Forencich
85e4f1d8ba Add PHY RX status output for a more reliable link up indication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:22:30 -07:00
Alex Forencich
a855fb3fb6 Use correct sync types 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:22:01 -07:00
Alex Forencich
a5934dae60 Add PTP timestamping tests to MACs and related modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:21:42 -07:00
Alex Forencich
e06eb07621 Set PTP CDC NS width to 6 in MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:20:42 -07:00
Alex Forencich
9012e25211 Fix PTP timestamp capture delay in axis_xgmii_tx_32 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:16:24 -07:00
Alex Forencich
7cb15647e7 Better handling of integrator saturation in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:15:31 -07:00
Alex Forencich
d96d5dfba0 Fix clock active detection in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:13:36 -07:00
Alex Forencich
7e5f6a2589 Remove extraneous code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 18:54:29 -07:00
Alex Forencich
4676296c49 Add block names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 18:51:27 -07:00
Alex Forencich
77617167fa Fix PTP TS FIFO instantiations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:34:54 -07:00
Alex Forencich
0ad02db4a8 Fix PTP timestamp capture in axis_xgmii_rx_32 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:18:02 -07:00
Alex Forencich
af0e15b241 Fix MAC RX PTP timestamp in sideband for axis_baser_rx_64 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:14:41 -07:00
Alex Forencich
2b33698f9b Fix alignment 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 13:25:13 -07:00
Alex Forencich
814a51a37c Use 128 KB RX RAM size for 25G designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 13:24:56 -07:00
Alex Forencich
827cb1ea1d Pipeline arbitration delay in muxes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:35:39 -07:00
Alex Forencich
01aa6a885b Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:32:28 -07:00
Alex Forencich
a020225304 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:30:14 -07:00
Alex Forencich
42cf40f338 merged changes in pcie 2022-05-15 19:27:48 -07:00
Alex Forencich
d685b0b125 Avoid width mismatch warning 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:26:10 -07:00
Alex Forencich
234c318ea1 Pipeline arbitration delay in muxes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:25:55 -07:00
Alex Forencich
ae1f4a9a22 Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:25:30 -07:00
Alex Forencich
48e525f62a merged changes in eth 2022-05-15 19:00:00 -07:00
Alex Forencich
80a25731b8 Fix MAC RX PTP timestamp in sideband 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:58:47 -07:00
Alex Forencich
8cdb780ee3 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:57:26 -07:00
Alex Forencich
4b261150d2 Update axis_arb_mux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:57:02 -07:00
Alex Forencich
609aac39a0 Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:47:30 -07:00
Alex Forencich
9b5a8cf24a Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:39:44 -07:00
Alex Forencich
794eb98789 merged changes in axis 2022-05-15 17:39:11 -07:00
Alex Forencich
ce8dcdafe8 Pipeline arbitration delay in axis_arb_mux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:36:26 -07:00
Alex Forencich
6d4458e5cc Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:36:00 -07:00
Alex Forencich
0845058419 Apparently iperf --bidir has issues with getting full BW on RX, so spin up separate TX and RX instances for TX+RX test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 15:03:02 -07:00
Alex Forencich
cadc811ec6 Set ptp4l tx_timestamp_timeout 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-14 23:54:54 -07:00
Alex Forencich
a897816b2c Add iperf_benchmark script 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 16:31:14 -07:00
Alex Forencich
37e9d5655d Add piperf wrapper script 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 16:27:59 -07:00
Alex Forencich
ed5b1a9b54 Add PCIe script directory symlink 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 16:27:37 -07:00
Alex Forencich
d575230c27 Fix race condition while taking down port 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 15:56:26 -07:00
Alex Forencich
268d0c66b8 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 12:57:41 -07:00
Alex Forencich
9653caf09b Add 25G mqnic design for Cisco Nexus K3P-Q 2022-05-09 14:02:13 -07:00
Alex Forencich
ba9ef590b7 Use Cisco Nexus part numbers for Cisco Nexus boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-09 13:43:47 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
6656a14528 merged changes in eth 2022-05-06 00:22:55 -07:00
Alex Forencich
18d5c325bf Fix CMAC RX PTP timestamps 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 23:21:11 -07:00
Alex Forencich
274831c268 Fix PTP clock CDC module timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 21:41:41 -07:00
Alex Forencich
1eb04bb75b utils: Improve PTP clock period reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 15:11:26 -07:00
Alex Forencich
7ee0a661bd modules/mqnic: Add kernel version check for ndetdev ioctl change 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 11:19:53 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
f67c704b11 Update placement constraints for hierarchy changes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-02 13:16:20 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00