334 Commits

Author	SHA1	Message	Date
Alex Forencich	0c1acadbfa	Enable termination on LVDS clock input	2021-02-05 22:12:59 -08:00
Alex Forencich	1d7dc703b5	Add cfgmclk timing constraints, rework reset connections	2021-02-05 18:00:56 -08:00
Alex Forencich	b16fe8f7e7	More XDC clean up, add IO delay constraints for low speed IO	2021-02-05 16:08:23 -08:00
Alex Forencich	89d7042aeb	Add CMS IP to all Alveo designs	2021-01-31 14:17:49 -08:00
Alex Forencich	722bd929b8	Placement updates	2021-01-31 12:48:49 -08:00
Alex Forencich	151ed7e179	Add extra reset registers	2021-01-31 11:10:03 -08:00
Alex Forencich	1248ca1a2e	Add power budget to Alveo XDC files	2021-01-29 15:44:15 -08:00
Alex Forencich	2a24722d7f	Add placement constraints for ADM-PCIE-9V3	2021-01-15 22:36:46 -08:00
Alex Forencich	972e41e433	Update placement constraints	2021-01-14 22:06:24 -08:00
Alex Forencich	93400bf05d	Update placement constraints for AU250 100G design	2021-01-14 17:19:40 -08:00
Alex Forencich	7ede1d38e6	Update placement constraints for VCU118 100G design	2021-01-14 16:50:21 -08:00
Alex Forencich	6476ad3fd0	Separate file for placement constraints	2021-01-14 14:42:58 -08:00
Alex Forencich	9accebffb9	Add pipeline registers, floorplanning constraints for AU200 100G design	2021-01-13 22:56:10 -08:00
Alex Forencich	9d97bf5a70	Add placement constraints for AU200 10G design	2021-01-13 22:14:18 -08:00
Alex Forencich	b2ce3e4602	Add placement constraints for VCU118 10G design	2021-01-13 21:49:55 -08:00
Alex Forencich	7d0cafeb18	Add placement constraints for AU250 10G design	2021-01-13 21:29:53 -08:00
Alex Forencich	96b3514207	Add placement constraints for VCU1525 10G design	2021-01-13 21:28:03 -08:00
Alex Forencich	7dba8c162c	Add placement constraints for AU280 10G design	2021-01-13 21:09:25 -08:00
Alex Forencich	8f8fbf33a8	Update placement constraints for AU280 100G design	2021-01-13 20:56:18 -08:00
Alex Forencich	42e19e1e96	Add pipeline registers, floorplanning constraints for VCU118 100G design	2021-01-13 20:55:20 -08:00
Alex Forencich	240ce56ccf	Add pipeline registers, floorplanning constraints for VCU1525 100G design	2021-01-13 20:54:42 -08:00
Alex Forencich	c0c2f933c0	Rework sim_build output directory, fix default makefile target	2020-12-29 17:28:53 -08:00
Alex Forencich	0c0fdc479b	Update testbenches for async send/recv	2020-12-18 17:40:36 -08:00
Alex Forencich	e3fb7d19b2	Fix PCIe config	2020-12-16 14:58:19 -08:00
Alex Forencich	b5ee772761	Migrate test infrastructure to cocotb	2020-12-15 16:52:20 -08:00
Alex Forencich	3240be1dd4	Add pipeline registers, floorplanning constraints for AU250 100G design	2020-12-03 15:08:57 -08:00
Alex Forencich	91edbbf3dc	Rename port and interface modules	2020-11-26 15:05:59 -08:00
Alex Forencich	53f4275ea2	Add output registers for I2C interface to improve timing	2020-10-13 23:52:52 -07:00
Alex Forencich	ac4859d88e	Fix user_clk_frequency setting in testbenches	2020-10-12 23:07:43 -07:00
Alex Forencich	7706df0d87	Fix bmc_led pin drive settings	2020-10-09 01:18:20 -07:00
Alex Forencich	d6810db7f5	Add extra output register for flash interface to improve routability and timing	2020-10-08 19:22:28 -07:00
Alex Forencich	b140d73660	Add PTP perout support to fb2CG@KU15P	2020-10-06 14:51:16 -07:00
Alex Forencich	4ebeab093e	Add 25G mqnic design for fb2CG@KU15P	2020-10-06 14:12:03 -07:00
Alex Forencich	993a712f01	Update VCU118 XDC	2020-10-06 00:41:45 -07:00
Alex Forencich	5ecfe4bcca	Update flash programming configuration for VCU118	2020-10-05 17:12:45 -07:00
Alex Forencich	c2ded31ab7	Add QSPI flash access and IPROG for VCU118	2020-10-05 17:06:12 -07:00
Alex Forencich	ba5aa5a82b	Fallback bitstream generation and flashing support	2020-10-04 00:40:59 -07:00
Alex Forencich	0f59f97f64	Add IPROG for ADM-PCIE-9V3	2020-10-03 21:07:54 -07:00
Alex Forencich	8ee9805473	Fix organization	2020-10-03 15:50:28 -07:00
Alex Forencich	3253164fec	Add IPROG for ExaNIC X25	2020-10-03 15:37:37 -07:00
Alex Forencich	8dfdf3a717	Add IPROG for ExaNIC X10	2020-10-03 15:36:40 -07:00
Alex Forencich	be67f173b6	Update flash programming configuration for ExaNIC X10 and X25	2020-10-03 15:32:21 -07:00
Alex Forencich	10357d97d4	Add BPI flash access and IPROG for VCU108	2020-10-02 20:44:47 -07:00
Alex Forencich	b57905eed6	Fix flash IDs	2020-10-02 20:30:05 -07:00
Alex Forencich	2a137bccbd	Fix flash programming commands for VCU108	2020-10-01 00:55:31 -07:00
Alex Forencich	91d0aaf8ae	Fix bitstream config for VCU1525	2020-09-30 23:51:11 -07:00
Alex Forencich	292ccb5627	Add QSPI flash access and IPROG for VCU1525	2020-09-29 21:20:40 -07:00
Alex Forencich	9dbac6d446	Add QSPI flash access and IPROG for Alveo	2020-09-29 21:12:05 -07:00
Alex Forencich	9c25a4523e	Add QSPI flash access and IPROG for fb2CG	2020-09-29 21:08:21 -07:00
Alex Forencich	1806a464bb	Update flash programming commands	2020-09-29 18:31:10 -07:00