334 Commits

Author	SHA1	Message	Date
Alex Forencich	5ddca32315	Fix flash settings	2020-09-29 17:32:06 -07:00
Alex Forencich	96f015d905	Update LED connections	2020-09-29 00:38:04 -07:00
Alex Forencich	4d6915fe2d	Update LED driver timing constraints	2020-09-28 17:25:23 -07:00
Alex Forencich	d29b1c7b91	Fix flash programming commands	2020-09-27 01:47:21 -07:00
Alex Forencich	b56e6200aa	Extra timing optimization for VCU108	2020-09-25 19:32:53 -07:00
Alex Forencich	6229e73044	Add missing i2c connections	2020-09-25 16:40:31 -07:00
Alex Forencich	94c2861de7	Use correct init_clk frequency	2020-09-23 14:25:48 -07:00
Alex Forencich	15022b3d94	Add 100G mqnic design for fb2CG@KU15P	2020-09-22 23:11:25 -07:00
Alex Forencich	1cd406f56f	Add 10G mqnic design for fb2CG@KU15P	2020-09-22 23:10:53 -07:00
Alex Forencich	72afcc44fe	Add 100G mqnic design for Alveo U250	2020-09-22 01:01:23 -07:00
Alex Forencich	5ddff9d17e	Add 100G mqnic design for Alveo U200	2020-09-22 01:01:07 -07:00
Alex Forencich	cbd7dbdbd5	Add 10G mqnic design for Alveo U250	2020-09-22 01:00:42 -07:00
Alex Forencich	6f72ac05b7	Add 10G mqnic design for Alveo U200	2020-09-22 01:00:23 -07:00
Alex Forencich	70b7082fb6	Implement new control registers	2020-09-19 17:25:58 -07:00
Alex Forencich	f8dca522a1	Add missing symlink	2020-08-20 12:26:24 -07:00
Alex Forencich	c8f5bb235c	Remove extraneous clock connections	2020-08-19 18:33:41 -07:00
Alex Forencich	171eb144cb	Update U280 placement constraints	2020-08-17 18:37:31 -07:00
Alex Forencich	e6b35f0567	Add PCIe mqnic design for ZCU106	2020-08-06 23:25:23 -07:00
Alex Forencich	e54eb685b3	Update makefiles	2020-08-06 18:43:47 -07:00
Alex Forencich	77b9cace47	Update BAR configuration in testbenches	2020-07-28 19:01:53 -07:00
Alex Forencich	ffd04d2bb0	Cleanup	2020-07-28 19:00:33 -07:00
Alex Forencich	d449be8fc5	Convert to 64 bit BARs	2020-07-24 16:54:57 -07:00
Alex Forencich	2a23be508a	Add 100G mqnic design for Alveo U50	2020-07-17 01:44:59 -07:00
Alex Forencich	deb895ff05	Add 10G mqnic design for Alveo U50	2020-07-17 01:44:28 -07:00
Alex Forencich	18f56fcb16	Remove extraneous signals	2020-07-17 00:57:47 -07:00
Alex Forencich	837a390567	Fix VCU118 CMAC reference clocks	2020-07-14 10:47:18 -07:00
Alex Forencich	20eac98bde	Clean up	2020-07-14 00:33:12 -07:00
Alex Forencich	e230fecb23	XDC clean up	2020-07-13 23:58:39 -07:00
Alex Forencich	9b7fa688d5	Add 100G mqnic design for Alveo U280	2020-07-12 11:33:28 -07:00
Alex Forencich	6433275139	Add 10G mqnic design for Alveo U280	2020-07-12 11:33:18 -07:00
Alex Forencich	f99736d4f5	Convert to TCL IP	2020-07-11 20:07:13 -07:00
Alex Forencich	50af74aa88	Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH	2020-04-20 18:43:26 -07:00
Alex Forencich	105a834790	Add mqnic design for NetFPGA SUME	2020-03-28 00:44:04 -07:00
Alex Forencich	9e3e80661c	Use common sync_reset module	2020-03-27 23:53:05 -07:00
Alex Forencich	ec03a36f98	Add 100G mqnic design for VCU118	2020-03-25 23:02:36 -07:00
Alex Forencich	239b7ddd0b	Add missing QSFP lpmode connections	2020-02-03 13:52:29 -08:00
Alex Forencich	63fcadaf0f	Add missing refclk control connections	2020-01-30 12:22:44 -08:00
Alex Forencich	70450a4d89	Add 100G mqnic design for VCU1525	2020-01-16 23:36:32 -08:00
Alex Forencich	26b7b67b9b	Add 10G mqnic design for VCU1525	2020-01-16 23:35:00 -08:00
Alex Forencich	e7cadac773	Remove extraneous files	2019-12-31 22:35:25 -08:00
Alex Forencich	81842e3c50	Add 100G mqnic design for Alpha Data board	2019-12-31 21:43:39 -08:00
Alex Forencich	a501f33c09	Update parameters	2019-12-29 16:46:25 -08:00
Alex Forencich	0955a4101f	Fix signal widths	2019-12-29 16:45:32 -08:00
Alex Forencich	7a68abbb84	Split control and data descriptor paths to DMA engine	2019-12-13 14:15:25 -08:00
Alex Forencich	88e31d0ccb	Connect PCIe credit interface to DMA cores	2019-12-13 12:41:50 -08:00
Alex Forencich	6270278c75	Add RSS support	2019-12-06 14:15:16 -08:00
Alex Forencich	0e7a91d927	Connect RQ sequence number	2019-12-03 18:19:17 -08:00
Alex Forencich	489506e4c0	Add FPGA ID register	2019-11-17 12:46:27 -08:00
Alex Forencich	445f80e6f2	Connect QSPI flash on Alpha Data board	2019-11-17 01:01:52 -08:00
Alex Forencich	33be402b16	Update widths	2019-11-14 00:02:10 -08:00