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Author SHA1 Message Date
Alex Forencich
e9d52516fb Unified 10G/25G design for ExaNIC X25 2022-03-14 19:12:58 -07:00
Alex Forencich
1fadd2f361 Unified 10G/25G design for ADM-PCIE-9V3 2022-03-14 18:50:40 -07:00
Alex Forencich
e5c6f7cf01 Unified 10G/25G design for fb2CG@KU15P 2022-03-14 17:44:31 -07:00
Alex Forencich
8168469ec8 Update config.tcl 2022-03-14 14:45:38 -07:00
Alex Forencich
4fc7e0b9d8 Use rsvg instead of inkscape for SVG conversion 2022-03-14 00:47:27 -07:00
Alex Forencich
f379d4225c Update readme 2022-03-13 23:44:11 -07:00
Alex Forencich
df8f3de64f Add requirements.txt for sphinx 2022-03-13 23:40:25 -07:00
Alex Forencich
1647377eb9 Update sphinx config 2022-03-13 23:35:14 -07:00
Alex Forencich
bc488dac9c Remove old block diagram 2022-03-13 23:33:34 -07:00
Alex Forencich
8345c1711d Update readme 2022-03-13 23:32:41 -07:00
Alex Forencich
1e601cff56 Initial commit of sphinx documentation 2022-03-13 23:32:01 -07:00
Alex Forencich
2ca96463fe Add driver debug print for number of configured IRQs 2022-03-04 23:55:51 -08:00
Alex Forencich
8fc832bbd2 Parametrization update 2022-03-04 15:37:49 -08:00
Alex Forencich
8e2e6c6026 Fix testbench 2022-03-04 00:01:33 -08:00
Alex Forencich
51877b2bfd Combined write and verify operation 2022-03-03 22:48:53 -08:00
Alex Forencich
d325d0df3e Minor cleanup 2022-03-03 22:48:24 -08:00
Alex Forencich
3d5395a7ca Update makefile 2022-03-03 22:46:18 -08:00
Alex Forencich
7fa621bddf Clean up types 2022-03-03 22:45:38 -08:00
Alex Forencich
e3799aa1bf Add missing dummy reads 2022-03-03 22:44:32 -08:00
Alex Forencich
d5f1da7f08 Print PCIe device ID, if available 2022-03-03 22:44:05 -08:00
Alex Forencich
d9e79c9923 Rename cores to match transceiver type 2022-03-03 22:41:34 -08:00
Alex Forencich
29f97dc663 Update ZCU106 to use new wrapper 2022-03-03 22:26:06 -08:00
Alex Forencich
a373753d6e Update VCU108 to use new wrapper 2022-03-03 22:23:43 -08:00
Alex Forencich
3ef15abcef Update VCU118 to use new wrapper 2022-03-03 22:14:18 -08:00
Alex Forencich
59eac3d2e5 Update ExaNIC X10 to use new wrapper 2022-03-03 20:38:55 -08:00
Alex Forencich
16111eb7a8 Update AU50 to use new wrapper 2022-03-03 20:15:06 -08:00
Alex Forencich
8fff75577a Update AU280 to use new wrapper 2022-03-03 19:53:49 -08:00
Alex Forencich
3472efd219 Update AU250 to use new wrapper 2022-03-03 17:49:08 -08:00
Alex Forencich
f8950897bc Update AU200 to use new wrapper 2022-03-03 17:34:42 -08:00
Alex Forencich
180ff33c7e Update VCU1525 to use new wrapper 2022-03-03 17:03:24 -08:00
Alex Forencich
37a4c41636 Update ADM-PCIE-9V3 to use new wrapper 2022-03-03 15:40:36 -08:00
Alex Forencich
7bbc777c98 Update ExaNIC X25 to use new wrapper 2022-03-03 15:32:17 -08:00
Alex Forencich
8851b3b1ad Add build automation scripts 2022-03-02 23:20:59 -08:00
Alex Forencich
2cc3dbd5cc Update DRP info 2022-03-02 23:12:02 -08:00
Alex Forencich
a54b673d54 Explicitly set equalizer mode 2022-03-02 23:11:49 -08:00
Alex Forencich
348aae9687 Update fb2CG@KU15P designs to use new wrapper 2022-03-02 17:38:47 -08:00
Alex Forencich
e91de95955 Fix rb_drp timing constraint for write enable signal 2022-03-02 17:31:17 -08:00
Alex Forencich
90d28ec9a2 Add common 10G PHY + GTH/GTY transceiver wrapper module 2022-03-02 17:28:40 -08:00
Alex Forencich
c799db69b4 Add PROGDIV_RATE register value defines 2022-03-02 17:26:02 -08:00
Alex Forencich
1378444d0c Add GTH and GTY transceiver DRP register definitions 2022-02-23 21:09:06 -08:00
Alex Forencich
614b391c48 Add DRP register block 2022-02-21 23:20:54 -08:00
Alex Forencich
65fbad93ca Fix parameter defaults 2022-02-20 00:13:35 -08:00
Alex Forencich
2909d205de Remove unused files 2022-02-16 17:40:28 -08:00
Alex Forencich
3997e0d95b Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter 2022-02-15 18:01:43 -08:00
Alex Forencich
1e4a88dea9 merged changes in pcie 2022-02-15 01:59:21 -08:00
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
a65b256b85 Update default SEG_ADDR_WIDTH parameter value for DMA RAM 2022-02-14 22:28:50 -08:00
Alex Forencich
66708ed6ff Add some more parameter checks 2022-02-14 00:41:28 -08:00
Alex Forencich
c98258bf05 Fix parametrization 2022-02-13 23:19:09 -08:00
Alex Forencich
627ac359d5 Add layer 2 ingress/egress modules 2022-02-13 23:09:41 -08:00