82 Commits

Author	SHA1	Message	Date
Alex Forencich	76fba3ac84	Add AXI central DMA module and testbenches	2018-12-06 17:27:44 -08:00
Alex Forencich	275cb09205	Minor reorganization	2018-12-06 17:19:30 -08:00
Alex Forencich	e5e2aa8867	Use correct parameter	2018-12-06 01:21:42 -08:00
Alex Forencich	e7b6f43c8c	Fix multi-driven net issue	2018-12-04 21:03:39 -08:00
Alex Forencich	7d0f3ef7a1	Fix address range overlap check to support arbitrary address widths	2018-12-04 17:00:26 -08:00
Alex Forencich	43234018cd	Add AXI read DMA module and testbenches	2018-12-03 23:29:22 -08:00
Alex Forencich	61df54e62d	Add M_REGIONS and M_SECURE parameters, add address range overlap check	2018-12-03 13:17:45 -08:00
Alex Forencich	7141a75ce8	Remove region inputs	2018-12-03 13:15:55 -08:00
Alex Forencich	b54d3eb866	Change cycle to segment, clean up parameters	2018-12-03 12:52:00 -08:00
Alex Forencich	0dbf0b1cff	Add optional output pipeline register to AXI RAM module	2018-11-27 01:17:31 -08:00
Alex Forencich	b289e02fe4	Remove extraneous code	2018-08-26 14:06:57 -07:00
Alex Forencich	71427e7cf0	Update default parameters	2018-08-26 14:05:10 -07:00
Alex Forencich	07a4da3bea	Fix connect logic	2018-08-23 16:20:58 -07:00
Alex Forencich	4f01dfb7d5	Support single slave interface	2018-08-23 14:43:57 -07:00
Alex Forencich	f1fb5b368c	Fix connect logic	2018-08-23 14:41:40 -07:00
Alex Forencich	a25c4b17eb	Add AXI shared interconnect and testbench	2018-08-22 23:42:31 -07:00
Alex Forencich	1753a2e6cf	Remove extraneous logic	2018-08-22 22:28:15 -07:00
Alex Forencich	8427aa12bf	Simplify request logic	2018-08-22 22:27:52 -07:00
Alex Forencich	0e36f647cb	Add arbiter and priority encoder modules	2018-08-22 21:50:31 -07:00
Alex Forencich	e696abbdff	Add AXI lite shared interconnect module and testbench	2018-08-22 20:34:31 -07:00
Alex Forencich	2a4c63e859	Change default address width to 32	2018-08-21 22:38:32 -07:00
Alex Forencich	6a002e2ce0	Add CONVERT_NARROW_BURST and FORWARD_ID parameters to AXI adapter	2018-08-20 23:23:00 -07:00
Alex Forencich	b15e8d9f63	Add AXI adapters and testbenchs	2018-08-20 19:10:08 -07:00
Alex Forencich	e06d607b85	Add AXI lite width adapter and testbenches	2018-08-16 16:37:11 -07:00
Alex Forencich	48577f3a2d	Add simple register as a per-channel option to AXI register modules	2018-08-16 13:25:07 -07:00
Alex Forencich	d541c64bc0	Add AXI lite registers and testbenches	2018-08-16 13:01:45 -07:00
Alex Forencich	ad453b12db	Add AXI lite RAM module and testbench	2018-08-14 23:49:40 -07:00
Alex Forencich	2113bb1795	Add AXI registers and testbenches	2018-08-13 23:36:47 -07:00
Alex Forencich	5f302d8106	Fix some more issues in AXI RAM module	2018-08-13 16:00:29 -07:00
Alex Forencich	66b20c171b	Add AXI FIFOs and testbenches	2018-08-13 15:31:04 -07:00
Alex Forencich	0cb456e047	Improve testbench and fix bugs in axi_ram	2018-08-11 22:32:05 -07:00
Alex Forencich	f4cca52660	Initial commit	2018-07-29 19:04:30 -07:00