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5 Commits

Author SHA1 Message Date
Alex Forencich
ef00d5ccfd Add parameters for FIFO output pipeline register depth 2021-09-02 14:45:18 -07:00
Alex Forencich
de869347cd Register interrupt signal 2021-09-01 13:14:02 -07:00
Alex Forencich
df9523011c Normalize instance names 2021-09-01 02:14:53 -07:00
Alex Forencich
37a558e4f6 Add pipeline FIFOs 2021-08-31 22:30:45 -07:00
Alex Forencich
bdbdc11841 Initial commit of core logic 2021-08-31 18:42:19 -07:00