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Author SHA1 Message Date
Alex Forencich
40a191a06d Add output FIFO and write done tracking to ultrascale PCIe read DMA interface 2021-02-24 13:50:05 -08:00
Alex Forencich
9c8417799d Add output FIFO and write done tracking to AXI stream sink DMA client 2021-02-24 13:48:56 -08:00
Alex Forencich
070689692d Add wr_done signal to RAM model and placeholders to DMA components 2021-02-24 13:47:53 -08:00
Alex Forencich
4b3d153cbd Add placement constraints for fb2CG@KU15P 2021-02-23 02:33:37 -08:00
Alex Forencich
2779087de9 Constrain DMA muxes to same SLR 2021-02-23 02:17:10 -08:00
Alex Forencich
ceebb9f20e Add more PCIe-related components to PCIe pblock 2021-02-23 00:55:05 -08:00
Alex Forencich
0afd441eba Fix active operation count logic 2021-02-17 21:14:51 -08:00
Alex Forencich
e5f5b1c352 Remove unused regs 2021-02-17 18:30:55 -08:00
Alex Forencich
68387161d4 Track active operation count to prevent status FIFO overflow 2021-02-17 18:29:44 -08:00
Alex Forencich
83b5d30347 Rewrite resets 2021-02-17 18:06:47 -08:00
Alex Forencich
057a93e07a Sync data handling 2021-02-16 13:56:44 -08:00
Alex Forencich
742ef1c272 Add same-width test cases to DMA clients 2021-02-16 01:26:05 -08:00
Alex Forencich
33bc8c21ae Fix bug in DMA client source when AXI stream width matches RAM interface width 2021-02-16 01:25:07 -08:00
Alex Forencich
20b2414d7a Use reg instead of next for read operation generation 2021-02-15 00:09:03 -08:00
Alex Forencich
93e2769269 Make 64-bit-only states no-ops for other interface widths 2021-02-14 15:17:28 -08:00
Alex Forencich
6ab66ed347 Fix signal name in xdc 2021-02-14 15:08:13 -08:00
Alex Forencich
a78674c06a Refactor TLP header and tuser computation 2021-02-14 11:16:25 -08:00
Alex Forencich
93496729f3 Update testbench 2021-02-12 16:59:13 -08:00
Alex Forencich
fb1d64e710 Add pipeline stage to dma_if_pcie_us_wr 2021-02-12 16:58:35 -08:00
Alex Forencich
6d98a7c0e6 Ensure output FIFOs use distributed RAM 2021-02-11 00:14:36 -08:00
Alex Forencich
5f7697178b Remove await ReadOnly 2021-02-10 18:42:32 -08:00
Alex Forencich
ba1b0ef20b Add output FIFO to write DMA interface module 2021-02-10 17:29:17 -08:00
Alex Forencich
f76ed26503 Add output FIFO to AXI stream source DMA client 2021-02-10 17:28:08 -08:00
Alex Forencich
c6d8983fcd Add wr_done output to DMA RAMs 2021-02-07 23:47:46 -08:00
Alex Forencich
633b47ef7f Update XDC files 2021-02-06 17:14:26 -08:00
Alex Forencich
c0c2dbce2a Update XDC files 2021-02-06 15:15:34 -08:00
Alex Forencich
ea093b0126 More XDC cleanup 2021-02-06 15:15:05 -08:00
Alex Forencich
46149bef3f Update ZCU106 XDC 2021-02-05 22:22:25 -08:00
Alex Forencich
24d179dd4a VCU118 XDC cleanup 2021-02-05 22:14:00 -08:00
Alex Forencich
0c1acadbfa Enable termination on LVDS clock input 2021-02-05 22:12:59 -08:00
Alex Forencich
1d7dc703b5 Add cfgmclk timing constraints, rework reset connections 2021-02-05 18:00:56 -08:00
Alex Forencich
b16fe8f7e7 More XDC clean up, add IO delay constraints for low speed IO 2021-02-05 16:08:23 -08:00
Alex Forencich
816689035c Add placement constraints for ADM-PCIE-9V3 2021-02-05 16:06:56 -08:00
Alex Forencich
9e27d45959 Add IPROG for ADM-PCIE-9V3 2021-02-05 16:06:34 -08:00
Alex Forencich
7c8abe261b Add driver support for Alveo BMC 2021-02-01 21:55:07 -08:00
Alex Forencich
8274d0b713 Minor refactor 2021-02-01 21:53:55 -08:00
Alex Forencich
9f970b1556 Use ETH_ALEN 2021-02-01 21:53:38 -08:00
Alex Forencich
6b142d36c2 Pull board-specific code into mqnic_board.c and refactor I2C code 2021-02-01 20:10:48 -08:00
Alex Forencich
53df02d22c Update makefile 2021-02-01 00:00:56 -08:00
Alex Forencich
df32217dc8 Use MAC list instead of base MAC for more flexibility 2021-01-31 22:25:24 -08:00
Alex Forencich
85d9ec7a87 Add mqnic-bmc tool 2021-01-31 21:32:57 -08:00
Alex Forencich
89d7042aeb Add CMS IP to all Alveo designs 2021-01-31 14:17:49 -08:00
Alex Forencich
722bd929b8 Placement updates 2021-01-31 12:48:49 -08:00
Alex Forencich
151ed7e179 Add extra reset registers 2021-01-31 11:10:03 -08:00
Alex Forencich
1248ca1a2e Add power budget to Alveo XDC files 2021-01-29 15:44:15 -08:00
Alex Forencich
4b28f527da Update readme 2021-01-16 13:43:42 -08:00
Alex Forencich
02c2f6d2b6 Update github actions 2021-01-16 13:42:04 -08:00
Alex Forencich
5d91fde42a Update github actions 2021-01-16 13:40:35 -08:00
Alex Forencich
eeb04acdd0 Update github actions 2021-01-16 13:39:56 -08:00
Alex Forencich
ac69ddfa22 Update github actions 2021-01-16 13:38:10 -08:00