Alex Forencich
|
aad30d09a1
|
Make FNS_WIDTH an internal parameter in PTP CDC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-09-21 16:30:29 -07:00 |
|
Alex Forencich
|
98b4fbb56d
|
Remove USE_SAMPLE_CLOCK parameter in PTP CDC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-09-18 16:58:02 -07:00 |
|
Alex Forencich
|
fa05d4ff3c
|
Add TX and RX enable inputs to MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-08-24 01:24:33 -07:00 |
|
Alex Forencich
|
20c542051d
|
Use cfg prefix for configuration signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-08-22 17:14:52 -07:00 |
|
Alex Forencich
|
2858aaaef7
|
Add TX PTP timestamp enable bit in tuser
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-07-17 10:58:40 -07:00 |
|
Alex Forencich
|
1f0b6a625c
|
PTP parameter clean-up
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-07-06 16:46:32 -07:00 |
|
Alex Forencich
|
77adf30dad
|
Add missing serdes_rx_reset_req output to 10G MAC+PHY modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-02-22 17:36:01 -08:00 |
|
Alex Forencich
|
5e528e0057
|
Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-11-01 23:56:11 -07:00 |
|
Alex Forencich
|
85e4f1d8ba
|
Add PHY RX status output for a more reliable link up indication
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-16 23:22:30 -07:00 |
|
Alex Forencich
|
a855fb3fb6
|
Use correct sync types
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-16 23:22:01 -07:00 |
|
Alex Forencich
|
e06eb07621
|
Set PTP CDC NS width to 6 in MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-16 23:20:42 -07:00 |
|
Alex Forencich
|
4676296c49
|
Add block names
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-16 18:51:27 -07:00 |
|
Alex Forencich
|
77617167fa
|
Fix PTP TS FIFO instantiations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-16 17:34:54 -07:00 |
|
Alex Forencich
|
6b18e56cb1
|
Add default_nettype none and resetall directives
|
2021-10-20 17:29:12 -07:00 |
|
Alex Forencich
|
786eabac4b
|
Add missing wires
|
2021-10-20 02:01:33 -07:00 |
|
Alex Forencich
|
c44e447db5
|
Transfer PTP information in tuser
|
2021-09-01 15:56:00 -07:00 |
|
Alex Forencich
|
e7de9b6ee6
|
Update PTP CDC instances
|
2021-08-26 01:07:56 -07:00 |
|
Alex Forencich
|
77938fa422
|
Update MAC modules for changes in FIFO modules
|
2021-08-26 00:55:12 -07:00 |
|
Alex Forencich
|
5e1329a992
|
Rework PHY bitslip timing
|
2021-05-05 00:35:43 -07:00 |
|
Alex Forencich
|
909ccae151
|
Properly synchronize bad FCS status output
|
2020-12-01 14:01:15 -08:00 |
|
Alex Forencich
|
591527f5a7
|
Pass through FIFO pipeline parameters
|
2020-09-07 13:26:34 -07:00 |
|
Alex Forencich
|
e9949f57a9
|
Remove extraneous code
|
2019-08-05 13:27:12 -07:00 |
|
Alex Forencich
|
ab77ac3858
|
Fix width
|
2019-07-19 18:16:07 -07:00 |
|
Alex Forencich
|
451db171d1
|
Don't leave output floating
|
2019-07-19 18:13:30 -07:00 |
|
Alex Forencich
|
16d1662d98
|
Add PTP timestamping infrastructure to 10G MACs
|
2019-07-18 23:13:46 -07:00 |
|
Alex Forencich
|
3bd7be44fa
|
Update FIFO instances and update MACs to use combined FIFO adapter module
|
2019-07-18 16:25:49 -07:00 |
|
Alex Forencich
|
134ce04777
|
Add configurable serdes pipeline register chain
|
2019-06-19 00:57:28 -07:00 |
|
Alex Forencich
|
79ec137243
|
Add PRBS31 generation and checking to 10G PHY
|
2019-05-10 20:28:45 -07:00 |
|
Alex Forencich
|
696c634726
|
Add rx_bad_block outputs
|
2019-04-17 00:16:45 -07:00 |
|
Alex Forencich
|
8285f94eaa
|
Rename tx_sync regs
|
2019-03-28 16:27:33 -07:00 |
|
Alex Forencich
|
3eaed305f5
|
Connect TX underflow status outputs
|
2019-03-28 16:27:15 -07:00 |
|
Alex Forencich
|
585ccefa15
|
Add TX underflow error signal
|
2019-03-26 12:42:08 -07:00 |
|
Alex Forencich
|
ec38440d89
|
Add 10G Ethernet MAC/PHY combination modules and testbenches
|
2019-01-31 18:13:07 -08:00 |
|