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Author SHA1 Message Date
Alex Forencich
f35d576301 Add mqnic-dump utility 2019-11-21 17:08:40 -08:00
Alex Forencich
317aa34db5 Expose control bits 2019-11-21 15:12:49 -08:00
Alex Forencich
e696433ecc Support changing MTU 2019-11-19 13:30:35 -08:00
Alex Forencich
2647f68124 Reset pointers after clearing buffers 2019-11-19 13:12:47 -08:00
Alex Forencich
463f2053b0 Add port register port_mtu 2019-11-18 16:30:32 -08:00
Alex Forencich
03465b4b25 Fix parameter 2019-11-18 16:27:02 -08:00
Alex Forencich
af434c8eba Add state_lock 2019-11-18 16:17:27 -08:00
Alex Forencich
489506e4c0 Add FPGA ID register 2019-11-17 12:46:27 -08:00
Alex Forencich
445f80e6f2 Connect QSPI flash on Alpha Data board 2019-11-17 01:01:52 -08:00
Alex Forencich
33be402b16 Update widths 2019-11-14 00:02:10 -08:00
Alex Forencich
bce2756c0c Parametrize checksum offload 2019-11-13 23:49:50 -08:00
Alex Forencich
334738a567 Set misc device parent to aid in device discovery 2019-11-10 14:44:20 -08:00
Alex Forencich
eddd7c3b03 Update makefile 2019-11-06 16:45:44 -08:00
Alex Forencich
f36773660d Set flash ID 2019-11-06 15:05:32 -08:00
Alex Forencich
8dd5d02e35 Add tx_queue_count field to mqnic_port, remove unnecessary arguments 2019-11-06 11:40:27 -08:00
Alex Forencich
ed7e374afa Remove obsolete driver code 2019-11-06 11:32:33 -08:00
Alex Forencich
0dc24a7baa Update readme 2019-11-05 22:13:26 -08:00
Alex Forencich
c954b55da9 Remove tx_scheduler_tdma_rr module 2019-11-05 22:10:47 -08:00
Alex Forencich
3655a6df00 Use new TDMA scheduler control module 2019-11-05 22:09:51 -08:00
Alex Forencich
93de8a1b32 Remove extraneous init code 2019-11-05 18:32:36 -08:00
Alex Forencich
e43c011e33 Update testbenches 2019-11-05 18:31:41 -08:00
Alex Forencich
7fb022abe1 Add tx_scheduler_ctrl_tdma module 2019-11-05 18:24:22 -08:00
Alex Forencich
29d223f0ab Add mqnic_sched struct 2019-11-05 18:21:08 -08:00
Alex Forencich
abdb714fd9 Read timeslot count 2019-11-05 18:20:21 -08:00
Alex Forencich
f53a6b20e8 Add timeslot count to port registers 2019-11-05 16:59:40 -08:00
Alex Forencich
f65b139797 Add scheduler control input to tx_scheduler_rr 2019-11-05 16:56:10 -08:00
Alex Forencich
304e0b7410 Update TDMA scheduler to generate status signals and avoid producing runt outputs 2019-11-05 16:55:19 -08:00
Alex Forencich
21e505386a Update mqnic-config 2019-11-05 16:51:28 -08:00
Alex Forencich
fa5e013255 Add MQNIC_MAX_SCHED define 2019-11-05 16:45:58 -08:00
Alex Forencich
e92485a41e Fix register definitions 2019-11-05 16:44:57 -08:00
Alex Forencich
cc592b44d7 Use correct PCIe core model 2019-11-04 14:13:12 -08:00
Alex Forencich
cf45a1b6fa Update port handling 2019-11-01 16:34:14 -07:00
Alex Forencich
381fd871c5 Parametrize tag widths 2019-10-31 23:25:34 -07:00
Alex Forencich
736321641f Parametrize addressing 2019-10-31 23:24:42 -07:00
Alex Forencich
d97407f245 merged changes in axi 2019-10-31 14:46:25 -07:00
Alex Forencich
7c69ab9e49 Add default addressing capability to interconnect modules 2019-10-31 14:44:26 -07:00
Alex Forencich
7583ce3ea3 Print addressing configuration 2019-10-30 23:22:45 -07:00
Alex Forencich
ed6f5b3655 Update overlap error message 2019-10-30 23:21:29 -07:00
Alex Forencich
4e95fb3677 Bypass check when unneeded 2019-10-30 22:57:56 -07:00
Alex Forencich
25454e712e Remove constant regs 2019-10-30 22:56:27 -07:00
Alex Forencich
f43cd09dac Add ExaNIC X25 mqnic design 2019-10-30 17:43:33 -07:00
Alex Forencich
533f19dfb7 merged changes in eth 2019-10-24 12:13:08 -07:00
Alex Forencich
9ef08c9d5d merged changes in axis 2019-10-24 12:09:16 -07:00
Alex Forencich
a9c04a4651 Fix frame FIFO drop 2019-10-24 12:08:08 -07:00
Alex Forencich
b3c654461e Update example design 2019-10-22 23:17:39 -07:00
Alex Forencich
407c2a3a62 merged changes in pcie 2019-10-22 16:07:47 -07:00
Alex Forencich
c43a3eb41a Fix latch inference 2019-10-22 16:03:58 -07:00
Alex Forencich
458a7fc598 Prioritize read request passthrough 2019-10-20 23:30:16 -07:00
Alex Forencich
771c3af93f Remove debug code 2019-10-20 23:21:21 -07:00
Alex Forencich
a65067d515 Update readme 2019-10-19 00:47:00 -07:00