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Author SHA1 Message Date
Alex Forencich
2325966973 Pull out descriptor and completion handling logic 2019-09-23 18:10:35 -07:00
Alex Forencich
6aa48f9127 Add completion op mux module 2019-09-23 14:47:09 -07:00
Alex Forencich
9219957013 Add descriptor op mux module 2019-09-23 14:47:00 -07:00
Alex Forencich
009a80aff2 Add completion write module 2019-09-23 14:44:08 -07:00
Alex Forencich
75a756e915 Add descriptor fetch module 2019-09-23 14:41:35 -07:00
Alex Forencich
835abf9412 Remove pcie_us_axi_master instances and corresponding BAR 2019-09-19 17:31:59 -07:00
Alex Forencich
b5868c8997 Update PTP perout support in VCU108 and VCU118 designs 2019-09-18 19:46:45 -07:00
Alex Forencich
49f9524aeb Update testbenches 2019-09-17 21:46:54 -07:00
Alex Forencich
e3ad96ef07 Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux 2019-09-17 16:32:47 -07:00
Alex Forencich
2e27d6ae2f Improve tx_scheduler_rr timing 2019-09-14 23:32:34 -07:00
Alex Forencich
d67a8616fa Enable all queues 2019-09-13 14:19:38 -07:00
Alex Forencich
49103b9df9 Rework interrupt handling 2019-09-13 13:53:36 -07:00
Alex Forencich
bee056e7d3 Fix pipelining bug 2019-09-13 13:48:48 -07:00
Alex Forencich
b59c3c50ed Rename int_index to eq_index 2019-09-12 16:06:22 -07:00
Alex Forencich
9341f93b3f Check PTP feature bits 2019-09-12 10:47:26 -07:00
Alex Forencich
132d44cd90 Increase crossbar threads count 2019-09-11 18:06:14 -07:00
Alex Forencich
a4bc99bb1b Fix parameters 2019-09-05 05:23:20 -07:00
Alex Forencich
5048864d86 Update tx_scheduler to handle out of order operations 2019-09-02 09:02:53 -07:00
Alex Forencich
e0a1e49d7b Update tx_engine to return status early in case of dequeue fail 2019-09-02 08:17:09 -07:00
Alex Forencich
7f33bf4982 Update rx_engine to return length 2019-09-02 08:15:07 -07:00
Alex Forencich
ce648698ce Enforce parameter range 2019-09-02 08:13:43 -07:00
Alex Forencich
bcfd665823 Connect queue index field in queue operation response 2019-09-01 08:29:22 -07:00
Alex Forencich
6d78315f81 Add queue index to queue operation response 2019-09-01 08:12:06 -07:00
Alex Forencich
364d835957 Split queue op tag table entry 2019-08-29 19:44:43 -07:00
Alex Forencich
ab07ab7ff7 Fix latch inference 2019-08-29 18:36:15 -07:00
Alex Forencich
d67c9ff70e Pull out scheduler op table size parameter 2019-08-23 07:44:33 -07:00
Alex Forencich
744ac22c75 Normalize queue op table sizes 2019-08-22 19:19:51 -07:00
Alex Forencich
6a354e7aa3 Normalize descriptor table sizes 2019-08-22 19:03:19 -07:00
Alex Forencich
5e0bf48b37 Update readme 2019-08-22 00:57:17 -07:00
Alex Forencich
3abb8d9534 Add TX checksum offload support to driver 2019-08-22 00:46:48 -07:00
Alex Forencich
a4132cfda7 Integrate TX checksum offload 2019-08-22 00:45:09 -07:00
Alex Forencich
3b6bca6b93 Add transmit checksum module and testbench 2019-08-21 22:57:41 -07:00
Alex Forencich
7b2a0d5032 Sync driver model 2019-08-20 01:36:22 -07:00
Alex Forencich
e548bd0238 Initialize RAMs 2019-08-20 01:06:29 -07:00
Alex Forencich
df4dbb75a1 Read interface feature bits in driver 2019-08-19 23:45:52 -07:00
Alex Forencich
d977cbdac2 Add feature bits 2019-08-19 23:43:52 -07:00
Alex Forencich
1fc15d234d Read interface and port features in userspace code 2019-08-19 23:29:09 -07:00
Alex Forencich
b77d21702a Read interface and port features in driver 2019-08-19 23:28:27 -07:00
Alex Forencich
5f066b9fcd Adjust ExaNIC board ID to match original PCIe ID 2019-08-19 22:04:10 -07:00
Alex Forencich
f5999faf60 Handle change in kernel API 2019-08-19 18:38:01 -07:00
Alex Forencich
35d73dde80 Add port activate and deactivate methods 2019-08-19 18:25:13 -07:00
Alex Forencich
7477cda192 Add port management code to userspace code 2019-08-19 16:00:29 -07:00
Alex Forencich
d8a2efc756 Add port management code to driver 2019-08-19 15:59:57 -07:00
Alex Forencich
0fd9bc7376 merged changes in pcie 2019-08-19 14:32:55 -07:00
Alex Forencich
68974e800b Fix completion handling bug 2019-08-19 14:31:08 -07:00
Alex Forencich
c9a17cdf90 Init scheduler queue state on reset 2019-08-13 13:51:50 -07:00
Alex Forencich
94c8dabad6 Rewrite scheduler 2019-08-13 00:45:01 -07:00
Alex Forencich
aeaabfeff5 Truncate high order address bits 2019-08-13 00:41:10 -07:00
Alex Forencich
80f06e1fcc Update testbenches 2019-08-13 00:39:28 -07:00
Alex Forencich
d99f40db08 Add port CSRs 2019-08-13 00:27:09 -07:00