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215 Commits

Author SHA1 Message Date
Alex Forencich
2858aaaef7 Add TX PTP timestamp enable bit in tuser 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 10:58:40 -07:00
Alex Forencich
905e6c6358 Add PTP timestamping tests for 1G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-08 01:41:35 -07:00
Alex Forencich
1f0b6a625c PTP parameter clean-up 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-06 16:46:32 -07:00
Alex Forencich
9159425cd8 Use correct payload lengths 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-29 22:18:50 -07:00
Alex Forencich
c65161e696 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:04:16 -08:00
Alex Forencich
ab0c382123 Rework parameter handling in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 21:03:16 -08:00
Alex Forencich
5e528e0057 Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:56:11 -07:00
Alex Forencich
c1e947dc3d Timing optimization of PTP modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:57:44 -07:00
Alex Forencich
a5934dae60 Add PTP timestamping tests to MACs and related modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:21:42 -07:00
Alex Forencich
6f2d581d62 Add output pipeline to PTP clock CDC module 2022-03-27 23:47:14 -07:00
Alex Forencich
945f22fd33 Add output pipeline to PTP clock module 2022-03-27 23:46:49 -07:00
Alex Forencich
0f2db26a8e Simplify logic in PTP clock module 2022-03-16 19:01:00 -07:00
Alex Forencich
23fb9d0bd8 Remove deprecated assignments 2022-03-16 18:43:36 -07:00
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
8bd6c8ea34 Remove some lint 2021-11-07 18:23:13 -08:00
Alex Forencich
32d99b4dd9 Use constants from cocotbext-eth 2021-11-07 18:21:06 -08:00
Alex Forencich
625c48c59c Add transceiver reset watchdog 2021-10-17 20:19:04 -07:00
Alex Forencich
a540e50e1c Fix XGMII to BASE-R control character mapping 2021-10-15 16:14:02 -07:00
Alex Forencich
a539a76ec4 Add cocotb testbenches for 10G MAC+PHY modules 2021-10-15 01:37:10 -07:00
Alex Forencich
e7dddc0dfd Add cocotb testbenches for AXI stream BASE-R TX and RX modules 2021-10-15 01:08:14 -07:00
Alex Forencich
8b95b33bab Add cocotb testbench for 10G PHY 2021-10-15 01:07:26 -07:00
Alex Forencich
2d9f01f9fe Add cocotb testbenches for XGMII BASE-R encoder and decoder modules 2021-10-15 01:06:57 -07:00
Alex Forencich
c0e2eb2b07 Add BASE-R serdes models for cocotb 2021-10-15 00:36:56 -07:00
Alex Forencich
c44e447db5 Transfer PTP information in tuser 2021-09-01 15:56:00 -07:00
Alex Forencich
77938fa422 Update MAC modules for changes in FIFO modules 2021-08-26 00:55:12 -07:00
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
5e1329a992 Rework PHY bitslip timing 2021-05-05 00:35:43 -07:00
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
00d69a341c Test with sample clock on and off 2021-03-27 14:44:36 -07:00
Alex Forencich
55359c1755 Report difference in ns 2021-03-27 14:44:21 -07:00
Alex Forencich
3cbe4b04da Improve timestamp difference measurement 2021-03-27 14:38:35 -07:00
Alex Forencich
2446001807 Add cocotb testbenche for arp 2021-03-08 22:52:11 -08:00
Alex Forencich
f21f6296ac Add cocotb testbenches for arp_eth_rx and arp_eth_tx 2021-03-08 22:51:27 -08:00
Alex Forencich
20a56dc0d6 Refactor eth_axis_rx and eth_axis_tx testbenches 2021-03-08 22:47:40 -08:00
Alex Forencich
4af058fbdc Update testbenches 2021-03-06 20:04:19 -08:00
Alex Forencich
22b3bacf51 Update attribute name 2021-03-05 23:03:41 -08:00
Alex Forencich
8e1ad2eba6 Add cocotb testbench for ptp_clock_cdc 2020-12-29 22:55:55 -08:00
Alex Forencich
7117de682a Add cocotb testbench for ptp_perout 2020-12-29 22:02:27 -08:00
Alex Forencich
0171afbb18 Add cocotb testbench for ptp_clock 2020-12-29 22:02:18 -08:00
Alex Forencich
e5bc5e1f49 Add cocotb testbench for arp_cache 2020-12-29 22:01:24 -08:00
Alex Forencich
25b890f8bb Remove extraneous code 2020-12-29 18:55:13 -08:00
Alex Forencich
77d22bfde0 Rework sim_build output directory, fix default makefile target 2020-12-29 14:47:12 -08:00
Alex Forencich
cd12721502 Add cococb testbenches for eth_axis_rx and eth_axis_tx 2020-12-28 19:28:38 -08:00
Alex Forencich
29dc7498d3 Add cocotb MAC testbenches 2020-12-28 19:26:46 -08:00
Alex Forencich
591527f5a7 Pass through FIFO pipeline parameters 2020-09-07 13:26:34 -07:00
Alex Forencich
4d4c7df5b6 Parametrize eth_axis_fcs 2020-05-05 16:13:02 -07:00
Alex Forencich
a55c354924 Parametrize Ethernet frame parsing 2020-02-21 21:37:57 -08:00
Alex Forencich
7994db90b1 Set initial tkeep state in testbenches 2020-02-21 15:18:21 -08:00
Alex Forencich
4ac6d6803b Parametrize ARP components 2020-02-20 16:49:47 -08:00
Alex Forencich
e9949f57a9 Remove extraneous code 2019-08-05 13:27:12 -07:00