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27 Commits

Author SHA1 Message Date
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
3d06b34679 fpga: Add DRAM bandwidth test to DMA benchmark application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-29 14:27:46 -07:00
Alex Forencich
d6bac395f3 fpga/app/dma_bench: Add DRAM test channel module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-29 14:23:52 -07:00
Alex Forencich
223c6c020d fpga/common: Add DRAM/HBM to core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-27 18:12:50 -07:00
Alex Forencich
b9945d3986 fpga/common: Pull out core_inst to simplify setup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-26 23:18:55 -07:00
Alex Forencich
1682389fd0 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:24:52 -08:00
Alex Forencich
e872c6c749 Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 23:20:44 -08:00
Alex Forencich
6c58e950d3 fpga/mqnic: Add DRAM interface module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-19 16:47:02 -08:00
Alex Forencich
e8aaadd102 fpga: Clean up top-level PCIe interface parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 23:56:56 -08:00
Alex Forencich
bee1703199 fpga/app/dma_bench: Refactor DMA benchmark application, use register blocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-30 23:26:05 -08:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
81648cf85b fpga/mqnic: Clean up PCIe DMA IF flow control connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:05 -07:00
Alex Forencich
e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:41 -07:00
Alex Forencich
33b798540e Change hex format in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:20:48 -07:00
Alex Forencich
729c3a0458 Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-08 22:07:18 -07:00
Alex Forencich
a5d7833bd9 Update testbenches for new version of cocotbext-pcie 2022-06-05 00:24:42 -07:00
Alex Forencich
21b0f014a5 Switch to MSI-X 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:58:29 -07:00
Alex Forencich
dd2853bf40 Update testbenches for latest version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-30 13:10:39 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00
Alex Forencich
53f3547ef5 Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-29 14:32:57 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
d45857fb98 fpga/app/dma_bench: Add DMA benchmark application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 14:19:43 -07:00