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461 Commits

Author SHA1 Message Date
Alex Forencich
64cdae1ccf fpga: Update designs for RX completion buffer management 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-31 10:26:40 -07:00
Alex Forencich
eb3343764d fpga/mqnic/DK_DEV_1SDX_P_A: Parameter clean-up 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-21 14:53:30 -07:00
Alex Forencich
47cfc828a2 fpga/mqnic/ADM_PCIE_9V3: Parameter clean-up, remove PCIE_TAG_COUNT from top level 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-19 13:34:33 -07:00
Alex Forencich
9834f8365c Rework resource management in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-01 22:04:43 -07:00
Alex Forencich
66f5b9fcc1 Clean up naming in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 21:48:34 -07:00
Alex Forencich
53d272ff12 fpga/mqnic/fb4CGg3: Add 25G mqnic design for Silicom fb4CGg3@VU09P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 13:55:58 -07:00
Alex Forencich
341115d70b fpga/mqnic/fb4CGg3: Add 100G mqnic design for Silicom fb4CGg3@VU09P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 13:51:57 -07:00
Alex Forencich
519330fd32 fpga: Move led_sreg_driver into common 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-27 14:12:42 -07:00
Alex Forencich
462d3c3a65 fpga/mqnic/fb2CG: Update led_sreg_driver to support interleaving and bit reversal 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-27 01:03:44 -07:00
Alex Forencich
04d137ffbc fpga/mqnic/DK_DEV_AGF014EA: Add notes on switch settings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 22:10:02 -07:00
Alex Forencich
587b4d5743 fpga/mqnic/DK_DEV_1SDX_P_A: Add 100G mqnic design for DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 22:07:32 -07:00
Alex Forencich
0634b86539 fpga/mqnic/DK_DEV_1SDX_P_A: Implement I2C interface on DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-22 20:24:50 -07:00
Alex Forencich
52068fbb31 fpga/mqnic: Rename Intel development kit designs based on part number 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-20 21:51:35 -07:00
Alex Forencich
526bcdb7b1 fpga/mqnic/DK_DEV_AGF014EA: Add 25G mqnic design for DK-DEV-AGF014EA 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-16 01:11:11 -07:00
Alex Forencich
19cbfeccaa fpga/mqnic/DK_DEV_AGF014EA: Add 100G mqnic design for DK-DEV-AGF014EA 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-16 01:10:43 -07:00
Alex Forencich
f4c016a46c fpga/mqnic/DE10-Agilex: Drop part suffix for production parts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:56:10 -07:00
Alex Forencich
14be62110e fpga/mqnic: Write compressed SOF files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:29:37 -07:00
Alex Forencich
adeb6d7a11 fpga/mqnic/DE10_Agilex: Report correct FPGA IDs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:26:39 -07:00
Alex Forencich
a3319d50b6 fpga/mqnic: Implement workaround for Quartus MLAB RAM read enable bug 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-14 01:21:36 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
c273b7f4ad mqnic: Register MIG resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-05 17:06:57 -07:00
Alex Forencich
f54fe4100a fpga/mqnic: Update Intel IP TCL files for E-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-30 13:50:59 -07:00
Alex Forencich
dd07e65330 fpga/mqnic/XUPP3R: Fix placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-30 00:10:59 -07:00
Alex Forencich
3d06b34679 fpga: Add DRAM bandwidth test to DMA benchmark application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-29 14:27:46 -07:00
Alex Forencich
7c6c39e446 fpga/mqnic: Move implementation strategy setting into config.tcl 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:40:12 -07:00
Alex Forencich
554369b33b fpga/mqnic: Update makefile path handling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:39:45 -07:00
Alex Forencich
853dca8c4c fpga/mqnic: Always create SLR pblocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:39:18 -07:00
Alex Forencich
1682389fd0 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:24:52 -08:00
Alex Forencich
e872c6c749 Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 23:20:44 -08:00
Alex Forencich
6c58e950d3 fpga/mqnic: Add DRAM interface module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-19 16:47:02 -08:00
Alex Forencich
5b20e3ff87 fpga/mqnic: Use BUFG for HBM AXI reset 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-18 13:55:00 -08:00
Alex Forencich
aee97e4825 fpga/mqnic: Add performance-related MIG settings to config.tcl 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 23:16:19 -08:00
Alex Forencich
7198973383 fpga/mqnic: Support using only a subset of HBM ports, and distribute subset across available interface ports for best performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 23:03:36 -08:00
Alex Forencich
9969b957d5 fpga/mqnic: Clean up HBM configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:56:12 -08:00
Alex Forencich
8672edfdb3 fpga/mqnic: Connect HBM MMCM reset input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:51:49 -08:00
Alex Forencich
1dacc6b1fa fpga/mqnic: Fix HBM temp signal width; tie off temp and cattrip signals when HBM is disabled 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:49:38 -08:00
Alex Forencich
c708bc45cd fpga/mqnic/fb2CG: Update testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:23:28 -08:00
Alex Forencich
e7dc033c78 fpga/mqnic/DE10_Agilex: Add DMA bench target for Terasic DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:18:40 -08:00
Alex Forencich
9020e0f819 fpga/mqnic/ZCU106: Add DMA bench target for Xilinx ZCU106 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:16:48 -08:00
Alex Forencich
76298b6cae fpga/mqnic/ZCU102: Add DMA bench target for Xilinx ZCU102 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:16:27 -08:00
Alex Forencich
0b9b9510ae fpga/mqnic/XUPP3R: Add DMA bench target for BittWare XUP-P3R 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:15:57 -08:00
Alex Forencich
23a5cc07da fpga/mqnic/VCU1525: Add DMA bench target for Xilinx VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:15:31 -08:00
Alex Forencich
6f49e42727 fpga/mqnic/VCU118: Add DMA bench target for Xilinx VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:15:15 -08:00
Alex Forencich
3483187403 fpga/mqnic/VCU108: Add DMA bench target for Xilinx VCU108 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:14:59 -08:00
Alex Forencich
014e810762 fpga/mqnic/NetFPGA_SUME: Add DMA bench target for NetFPGA SUME 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:14:32 -08:00
Alex Forencich
c306d20669 fpga/mqnic/Nexus_K3P_Q: Add DMA bench target for Cisco Nexus K3P-Q 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:14:02 -08:00
Alex Forencich
f9f4415e13 fpga/mqnic/Nexus_K3P_S: Add DMA bench target for Cisco Nexus K3P-S 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:13:47 -08:00
Alex Forencich
2672f39115 fpga/mqnic/Nexus_K35_S: Add DMA bench target for Cisco Nexus K35-S 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:13:15 -08:00
Alex Forencich
b915babce8 fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP: Add DMA bench target for Dini Group DNPCIe_40G_KU_LL_2QSFP 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:12:25 -08:00
Alex Forencich
76553e3bba fpga/mqnic/250_SoC: Add DMA bench target for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:10:53 -08:00