Alex Forencich
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64cdae1ccf
|
fpga: Update designs for RX completion buffer management
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-31 10:26:40 -07:00 |
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Alex Forencich
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9834f8365c
|
Rework resource management in testbenches, driver, and utils
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-01 22:04:43 -07:00 |
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Alex Forencich
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66f5b9fcc1
|
Clean up naming in testbenches, driver, and utils
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-30 21:48:34 -07:00 |
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Alex Forencich
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519330fd32
|
fpga: Move led_sreg_driver into common
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-27 14:12:42 -07:00 |
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Alex Forencich
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462d3c3a65
|
fpga/mqnic/fb2CG: Update led_sreg_driver to support interleaving and bit reversal
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-27 01:03:44 -07:00 |
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Alex Forencich
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bb158d568f
|
Add RX indirection table
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-04-10 15:05:32 -07:00 |
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Alex Forencich
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c273b7f4ad
|
mqnic: Register MIG resets
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-04-05 17:06:57 -07:00 |
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Alex Forencich
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3d06b34679
|
fpga: Add DRAM bandwidth test to DMA benchmark application
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-03-29 14:27:46 -07:00 |
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Alex Forencich
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554369b33b
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fpga/mqnic: Update makefile path handling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-03-24 00:39:45 -07:00 |
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Alex Forencich
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1682389fd0
|
Remove recursively-expanded macros for module parameters in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-02-17 16:24:52 -08:00 |
|
Alex Forencich
|
e872c6c749
|
Rework parameter handling in testbench makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-01-29 23:20:44 -08:00 |
|
Alex Forencich
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6c58e950d3
|
fpga/mqnic: Add DRAM interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-12-19 16:47:02 -08:00 |
|
Alex Forencich
|
aee97e4825
|
fpga/mqnic: Add performance-related MIG settings to config.tcl
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-12-17 23:16:19 -08:00 |
|
Alex Forencich
|
c708bc45cd
|
fpga/mqnic/fb2CG: Update testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-12-06 17:23:28 -08:00 |
|
Alex Forencich
|
e8aaadd102
|
fpga: Clean up top-level PCIe interface parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-12-04 23:56:56 -08:00 |
|
Alex Forencich
|
0644a12a48
|
fpga/mqnic: Remove extraneous top-level parameter RX_RSS_ENABLE from config.tcl scripts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-12-03 21:32:51 -08:00 |
|
Alex Forencich
|
347a03b347
|
fpga/mqnic: Rework PCIe IP core configuration, fixes disrupted MSI-X settings with application section enabled and issues with PCIe class code on 7-series and UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-12-03 18:16:12 -08:00 |
|
Alex Forencich
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c5003d0c6d
|
fpga/mqnic: Select advanced mode for Xilinx PCIe IP core config to access MSI-X settings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-12-03 15:35:16 -08:00 |
|
Alex Forencich
|
bee1703199
|
fpga/app/dma_bench: Refactor DMA benchmark application, use register blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-11-30 23:26:05 -08:00 |
|
Alex Forencich
|
f70f4d9b90
|
Use CMAC wrapper in 100G mqnic design for fb2CG@KU15P
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-11-10 11:42:07 -08:00 |
|
Alex Forencich
|
8c733dff9e
|
fpga/mqnic/fb2CG: Update placement constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-17 13:01:16 -07:00 |
|
Alex Forencich
|
e3f2d8990d
|
fpga/mqnic: Use all ports for TDMA designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-15 23:30:54 -07:00 |
|
Alex Forencich
|
d3942da875
|
fpga: Add clock info register block
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-15 19:45:02 -07:00 |
|
Alex Forencich
|
6fa30bc94c
|
fpga/mqnic: Fix critical warnings when MIGs are not present
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-15 13:47:41 -07:00 |
|
Alex Forencich
|
d0cc106783
|
fpga: Remove redundant RX_RSS_ENABLE parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-13 17:10:25 -07:00 |
|
Alex Forencich
|
01df80df86
|
fpga/mqnic: Disable MIGs by default
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-12 23:57:27 -07:00 |
|
Alex Forencich
|
5e52a52f5e
|
fpga/mqnic: Add MIGs and HBM controllers for most boards
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-12 19:00:49 -07:00 |
|
Alex Forencich
|
eb990643f2
|
fpga/mqnic: various minor cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-12 17:12:07 -07:00 |
|
Alex Forencich
|
5f1e74b0e1
|
Add PROJECT variable, remove multiple stem matches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-11 13:33:09 -07:00 |
|
Alex Forencich
|
7017e7d49b
|
Explicitly set top module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-11 12:29:01 -07:00 |
|
Alex Forencich
|
ceb6a9ca06
|
Update clean target
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-11 12:26:39 -07:00 |
|
Alex Forencich
|
9c98f12392
|
Write debug probes file alongside bit file
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-10 23:37:54 -07:00 |
|
Alex Forencich
|
9628401780
|
Normalize output file location
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-10 21:47:53 -07:00 |
|
Alex Forencich
|
caf2a0993b
|
fpga: Output hierarchical utilization reports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-06 21:17:25 -07:00 |
|
Alex Forencich
|
d7904b8007
|
fpga: Add support for IRQ rate limiting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-04 15:24:40 -07:00 |
|
Alex Forencich
|
1486da601f
|
fpga: Add clock period parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-04 12:03:35 -07:00 |
|
Alex Forencich
|
81648cf85b
|
fpga/mqnic: Clean up PCIe DMA IF flow control connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-03 23:04:05 -07:00 |
|
Alex Forencich
|
c76e152804
|
Rename cmac_ts_insert to mac_ts_insert
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-18 22:27:27 -07:00 |
|
Alex Forencich
|
ef5b2449dc
|
Add stretched PTP PPS output
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-18 22:25:58 -07:00 |
|
Alex Forencich
|
676f3edd2d
|
Add TX PTP clock to port map module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-18 22:25:39 -07:00 |
|
Alex Forencich
|
e0d92172d3
|
Separate PTP TX clock input
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-18 22:24:41 -07:00 |
|
Alex Forencich
|
33b798540e
|
Change hex format in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-09 14:20:48 -07:00 |
|
Alex Forencich
|
729c3a0458
|
Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-08 22:07:18 -07:00 |
|
Alex Forencich
|
a5d7833bd9
|
Update testbenches for new version of cocotbext-pcie
|
2022-06-05 00:24:42 -07:00 |
|
Alex Forencich
|
21b0f014a5
|
Switch to MSI-X
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-06-02 23:58:29 -07:00 |
|
Alex Forencich
|
dd2853bf40
|
Update testbenches for latest version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-30 13:10:39 -07:00 |
|
Alex Forencich
|
5da044826d
|
Add board-level configuration parameter for TDMA BER module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-18 11:25:58 -07:00 |
|
Alex Forencich
|
ed2d34153d
|
Use PHY rx_status signal for link status detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-17 00:46:05 -07:00 |
|
Alex Forencich
|
814a51a37c
|
Use 128 KB RX RAM size for 25G designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-16 13:24:56 -07:00 |
|
Alex Forencich
|
835f0d38f0
|
Update PTP subsystem to use separate clock for improved stability
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-06 17:46:16 -07:00 |
|