Alex Forencich
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64cdae1ccf
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fpga: Update designs for RX completion buffer management
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-31 10:26:40 -07:00 |
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Alex Forencich
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9834f8365c
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Rework resource management in testbenches, driver, and utils
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-01 22:04:43 -07:00 |
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Alex Forencich
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66f5b9fcc1
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Clean up naming in testbenches, driver, and utils
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-30 21:48:34 -07:00 |
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Alex Forencich
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53d272ff12
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fpga/mqnic/fb4CGg3: Add 25G mqnic design for Silicom fb4CGg3@VU09P
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-30 13:55:58 -07:00 |
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Alex Forencich
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341115d70b
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fpga/mqnic/fb4CGg3: Add 100G mqnic design for Silicom fb4CGg3@VU09P
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-30 13:51:57 -07:00 |
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