7 Commits

Author	SHA1	Message	Date
Alex Forencich	f8bc6c31e5	Update AXI master modules to support 512 bit interface	2019-10-14 16:20:46 -07:00
Alex Forencich	e97e4ad423	Parametrize tuser signal widths	2019-09-26 23:30:03 -07:00
Alex Forencich	c75f29c648	Add parameter documentation	2019-07-24 18:01:13 -07:00
Alex Forencich	89c52d4eec	Fix bit width warning	2018-11-26 23:27:06 -08:00
Alex Forencich	008a7167c7	Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master	2018-11-26 18:03:54 -08:00
Alex Forencich	31e43ff7c1	Add enable and drop ports to CQ demux	2018-10-29 16:28:26 -07:00
Alex Forencich	4c9c493aa4	Add Ultrascale PCIe AXI master module and testbenches	2018-10-23 22:28:06 -07:00