Alex Forencich
f687aba432
fpga/mqnic: Update designs to use port mapping modules
...
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-04-13 01:37:10 -07:00
Alex Forencich
57905a5ef9
fpga/mqnic/ZCU106/fpga_zynqmp: Rewrite zynq PS TCL script, rework PS clock settings, switch to 300 MHz PL clock
...
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-04-11 12:25:51 -07:00
Alex Forencich
72d8583235
fpga/mqnic/ZCU106/fpga_zynqmp: Remove unused I2C interface
...
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-04-11 10:54:58 -07:00
Alex Forencich
c5d5fe8a64
fpga/mqnic: Remove unused wires
...
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-04-09 23:02:44 -07:00
Alex Forencich
5f7c051b5b
ZCU106/fpga_zynqmp: Sync module parameters
...
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-04-07 21:41:06 -07:00
Joachim Foerster
62879ff3ea
ZCU106/fpga_zynqmp: Support parameter EVENT_QUEUE_INDEX_WIDTH, reduce Events queues to number of CPU cores
...
- Keep parameter defaults in Verilog file at global of 32, though
- Select 4 Event queues via config.tcl, only
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
2022-03-31 17:24:16 +02:00
Andreas Braun
35517037e6
ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1
...
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Förster <joachim.foerster@missinglinkelectronics.com>
2022-03-31 17:22:27 +02:00
