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Author SHA1 Message Date
Alex Forencich
f6da532b97 Read PHC stride 2019-12-30 21:02:24 -08:00
Alex Forencich
8aeea9e110 Add perout offset and stride defines 2019-12-30 20:45:56 -08:00
Alex Forencich
f642bb7f7e Reserve packet data slot early and release on dequeue fail 2019-12-30 17:49:42 -08:00
Alex Forencich
91a538ff5f Change driver queue count limits 2019-12-29 23:40:07 -08:00
Alex Forencich
3737d85206 Use correct queue counts 2019-12-29 17:07:04 -08:00
Alex Forencich
a501f33c09 Update parameters 2019-12-29 16:46:25 -08:00
Alex Forencich
0955a4101f Fix signal widths 2019-12-29 16:45:32 -08:00
Alex Forencich
3690fdeb7d Pull out pipeline parameters 2019-12-28 01:16:16 -08:00
Alex Forencich
58200e9851 Fix testbench 2019-12-28 01:15:40 -08:00
Alex Forencich
db9e1df1fa Update pipelining to enable URAM inference 2019-12-28 01:13:57 -08:00
Alex Forencich
f97ff4407b Change driver model max packet size 2019-12-23 14:41:52 -08:00
Alex Forencich
cbde1abaf9 Add CMAC pad module 2019-12-23 14:40:51 -08:00
Alex Forencich
96bb5feead merged changes in pcie 2019-12-23 14:39:18 -08:00
Alex Forencich
45a33b8293 Fix scheduler bug 2019-12-16 14:13:01 -08:00
Alex Forencich
e14f6c6f0e Remove unused signals 2019-12-13 15:33:12 -08:00
Alex Forencich
dfd9744b3e PCIe DMA write bandwidth optimizations 2019-12-13 15:31:37 -08:00
Alex Forencich
7a68abbb84 Split control and data descriptor paths to DMA engine 2019-12-13 14:15:25 -08:00
Alex Forencich
88e31d0ccb Connect PCIe credit interface to DMA cores 2019-12-13 12:41:50 -08:00
Alex Forencich
59d39ca7ec merged changes in pcie 2019-12-07 18:53:55 -08:00
Alex Forencich
a6d64bbcbb Remove extraneous character 2019-12-07 14:36:32 -08:00
Alex Forencich
d561195dc8 Add get_data_credits to TLP 2019-12-07 00:54:16 -08:00
Alex Forencich
7567db1818 Add credit-based flow control to DMA cores 2019-12-06 23:24:36 -08:00
Alex Forencich
00858212c6 Placeholder values for flow control credit outputs 2019-12-06 19:16:05 -08:00
Alex Forencich
04a3d24ffc Update readme 2019-12-06 14:56:54 -08:00
Alex Forencich
4dafedca27 Reschedule queue if necessary 2019-12-06 14:21:20 -08:00
Alex Forencich
6270278c75 Add RSS support 2019-12-06 14:15:16 -08:00
Alex Forencich
60a2813fbc Fix indentation 2019-12-05 22:09:04 -08:00
Alex Forencich
bcd45fe9f2 Name IRQs 2019-12-05 16:24:46 -08:00
Alex Forencich
b5d7bd15b4 Add rx_hash module and testbenches 2019-12-05 13:47:07 -08:00
Alex Forencich
2fa4f595ee Don't crash with a null device pointer 2019-12-04 13:37:53 -08:00
Alex Forencich
90e2f8f5d0 Check if FPGA needs reset in utilities 2019-12-04 13:37:18 -08:00
Alex Forencich
ef365b9bab Report which ring is full 2019-12-04 13:36:19 -08:00
Alex Forencich
384912e618 Improve sanity checking and error reporting in receive handling 2019-12-04 13:34:56 -08:00
Alex Forencich
c4d17b6a3c Improve sanity checking and error reporting in event queue processing 2019-12-04 13:32:46 -08:00
Alex Forencich
a432a8f472 Dump event queue state 2019-12-04 13:29:40 -08:00
Alex Forencich
0e7a91d927 Connect RQ sequence number 2019-12-03 18:19:17 -08:00
Alex Forencich
936cfd9524 merged changes in pcie 2019-12-03 15:48:38 -08:00
Alex Forencich
f3a6cec13a Use nonblocking assign 2019-12-03 15:47:58 -08:00
Alex Forencich
8985c6dbf3 Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules 2019-12-03 15:46:36 -08:00
Alex Forencich
a1d0fb810f Reorganize 2019-12-02 15:27:27 -08:00
Alex Forencich
2afef8c6d8 Fix use before define 2019-12-02 15:18:08 -08:00
Alex Forencich
80dafd5870 Check FIFO depth 2019-12-02 15:15:24 -08:00
Alex Forencich
2dbe6e19ab Reset mask FIFO pointers 2019-12-02 14:07:17 -08:00
Alex Forencich
a7be8e8f87 Clear the sequence number valid bits 2019-11-27 16:43:15 -08:00
Alex Forencich
546ef162dd Rewrite reset 2019-11-26 16:44:46 -08:00
Alex Forencich
4c8fcef230 Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules 2019-11-26 16:30:30 -08:00
Alex Forencich
c5a0d05b47 Add OP_TABLE_SIZE parameter to testbenches 2019-11-26 00:00:49 -08:00
Alex Forencich
e7bd0a62f1 Implement RQ sequence numbers in Ultrascale models 2019-11-25 18:07:49 -08:00
Alex Forencich
bbcdcc17bc Rename OP_TAG_WIDTH to OP_TABLE_SIZE 2019-11-25 14:59:53 -08:00
Alex Forencich
176e1159a3 Update python parameter computation to match verilog clog2 2019-11-24 00:01:33 -08:00