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307 Commits

Author SHA1 Message Date
Alex Forencich
f705646e3e Pull out header size as a parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-29 15:48:39 -07:00
Alex Forencich
77adf30dad Add missing serdes_rx_reset_req output to 10G MAC+PHY modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-22 17:36:01 -08:00
Alex Forencich
450765187e Update lfsr.v 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-15 12:36:03 -08:00
Alex Forencich
cb1dc8fb15 Optimize FCS verification in 10G/25G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-13 15:47:30 -08:00
Alex Forencich
713b138ece Fix timing of IDDR2 on Spartan 6 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-01 21:44:15 -08:00
Alex Forencich
a1abc97e2a ISE does not support clog2 in localparam 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-27 18:26:47 -08:00
Alex Forencich
2199a15c75 Force possible floating point parameter value to integer when taking clog2 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:56:27 -07:00
Alex Forencich
5e528e0057 Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:56:11 -07:00
Alex Forencich
e542d39a75 Fix assignment type 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-20 09:21:34 -07:00
Alex Forencich
40acee1bc5 Rework MAC PTP timestamp adjustment logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 16:35:26 -07:00
Alex Forencich
07aeae5c2f Rework lane swapping logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 15:06:09 -07:00
Alex Forencich
fbaa714d2a Remove unnecessary CRC resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 15:03:03 -07:00
Alex Forencich
cb273970c3 Rework MAC frame padding logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 22:46:03 -07:00
Alex Forencich
2ce89aec09 Use generate blocks for Ethernet FCS computation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 19:52:55 -07:00
Alex Forencich
5f39d6ece6 Improve internal encoding to simplify logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 17:32:43 -07:00
Alex Forencich
c7f3b4632b Simplify logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 16:08:34 -07:00
Alex Forencich
2601127679 Remove unnecessary zeroing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 14:09:09 -07:00
Alex Forencich
ebd5f04e2d Remove unnecessary resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 10:14:54 -07:00
Alex Forencich
c1e947dc3d Timing optimization of PTP modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:57:44 -07:00
Alex Forencich
db881ed551 Remove magic numbers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 18:39:21 -07:00
Alex Forencich
4a16c9070b Fix mixed assignments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 01:24:22 -07:00
Alex Forencich
85e4f1d8ba Add PHY RX status output for a more reliable link up indication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:22:30 -07:00
Alex Forencich
a855fb3fb6 Use correct sync types 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:22:01 -07:00
Alex Forencich
e06eb07621 Set PTP CDC NS width to 6 in MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:20:42 -07:00
Alex Forencich
9012e25211 Fix PTP timestamp capture delay in axis_xgmii_tx_32 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:16:24 -07:00
Alex Forencich
7cb15647e7 Better handling of integrator saturation in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:15:31 -07:00
Alex Forencich
d96d5dfba0 Fix clock active detection in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:13:36 -07:00
Alex Forencich
7e5f6a2589 Remove extraneous code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 18:54:29 -07:00
Alex Forencich
4676296c49 Add block names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 18:51:27 -07:00
Alex Forencich
77617167fa Fix PTP TS FIFO instantiations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:34:54 -07:00
Alex Forencich
0ad02db4a8 Fix PTP timestamp capture in axis_xgmii_rx_32 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:18:02 -07:00
Alex Forencich
af0e15b241 Fix MAC RX PTP timestamp in sideband for axis_baser_rx_64 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:14:41 -07:00
Alex Forencich
80a25731b8 Fix MAC RX PTP timestamp in sideband 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:58:47 -07:00
Alex Forencich
609aac39a0 Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:47:30 -07:00
Alex Forencich
9b5a8cf24a Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:39:44 -07:00
Alex Forencich
6f2d581d62 Add output pipeline to PTP clock CDC module 2022-03-27 23:47:14 -07:00
Alex Forencich
945f22fd33 Add output pipeline to PTP clock module 2022-03-27 23:46:49 -07:00
Alex Forencich
108c02d721 Simplify logic in PTP clock CDC module 2022-03-16 19:01:17 -07:00
Alex Forencich
0f2db26a8e Simplify logic in PTP clock module 2022-03-16 19:01:00 -07:00
Alex Forencich
7d8b5560b7 Fix backpressure bug 2021-12-31 22:58:38 -08:00
Alex Forencich
853c1737aa Simplify logic 2021-12-31 22:57:11 -08:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
786eabac4b Add missing wires 2021-10-20 02:01:33 -07:00
Alex Forencich
625c48c59c Add transceiver reset watchdog 2021-10-17 20:19:04 -07:00
Alex Forencich
7594ac0775 Init and reset to same value 2021-10-17 02:13:14 -07:00
Alex Forencich
9d4d8508ae Unconditionally pass through ordered set data to simplify decode logic 2021-10-16 01:25:48 -07:00
Alex Forencich
247aeae845 Detect bad XGMII encodings in PHY TX 2021-10-16 00:50:48 -07:00
Alex Forencich
3b2e6874d8 Rework XGMII to BASE-R encoder implementation 2021-10-16 00:48:01 -07:00
Alex Forencich
9667ef1f9c Detect sequence errors 2021-10-16 00:03:35 -07:00
Alex Forencich
5258bdc312 Improve bad block detection 2021-10-15 23:58:35 -07:00