Alex Forencich
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d3942da875
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fpga: Add clock info register block
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-15 19:45:02 -07:00 |
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Alex Forencich
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d0cc106783
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fpga: Remove redundant RX_RSS_ENABLE parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-13 17:10:25 -07:00 |
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Alex Forencich
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941288e926
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fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 17:12:23 -07:00 |
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Alex Forencich
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d7904b8007
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fpga: Add support for IRQ rate limiting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-04 15:24:40 -07:00 |
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Alex Forencich
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1486da601f
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fpga: Add clock period parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-04 12:03:35 -07:00 |
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Alex Forencich
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81648cf85b
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fpga/mqnic: Clean up PCIe DMA IF flow control connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 23:04:05 -07:00 |
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Alex Forencich
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ef5b2449dc
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Add stretched PTP PPS output
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-18 22:25:58 -07:00 |
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Alex Forencich
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e0d92172d3
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Separate PTP TX clock input
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-18 22:24:41 -07:00 |
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Alex Forencich
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33b798540e
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Change hex format in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-09 14:20:48 -07:00 |
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Alex Forencich
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729c3a0458
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Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-08 22:07:18 -07:00 |
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Alex Forencich
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a5d7833bd9
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Update testbenches for new version of cocotbext-pcie
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2022-06-05 00:24:42 -07:00 |
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Alex Forencich
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21b0f014a5
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Switch to MSI-X
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-02 23:58:29 -07:00 |
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Alex Forencich
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dd2853bf40
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Update testbenches for latest version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-30 13:10:39 -07:00 |
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Alex Forencich
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835f0d38f0
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Update PTP subsystem to use separate clock for improved stability
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-06 17:46:16 -07:00 |
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Alex Forencich
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c2fea3a616
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Add port register blocks with support for PHY link status reporting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-04 09:03:37 -07:00 |
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Alex Forencich
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cfdd6f5455
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Decouple transmit completion handling from PTP timestamping
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-01 17:41:47 -07:00 |
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Alex Forencich
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53f3547ef5
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Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-29 14:32:57 -07:00 |
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Alex Forencich
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2d5e82f42a
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apps: Fix application module symbol search path to include core mqnic module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-25 00:48:56 -07:00 |
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Alex Forencich
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2bd8350276
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Add RX queue mapping module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-23 00:12:22 -07:00 |
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Alex Forencich
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d45857fb98
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fpga/app/dma_bench: Add DMA benchmark application
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-21 14:19:43 -07:00 |
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