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Author SHA1 Message Date
Alex Forencich
fab74d1d0f Update test durations 2021-11-02 18:29:35 -07:00
Alex Forencich
47a2570647 Set class code to memory controller, set subsystem ID based on board 2021-11-02 14:39:33 -07:00
Alex Forencich
ad157ca3ad Enable interrupts 2021-11-02 14:35:42 -07:00
Alex Forencich
38358ffa43 Print subsystem IDs 2021-11-02 14:35:25 -07:00
Alex Forencich
f612d88288 Rewrite op tag FIFO read in DMA engines 2021-10-31 21:57:26 -07:00
Alex Forencich
482b305913 Fix 64-bit TLP address forcing logic in generic interface model 2021-10-27 17:54:41 -07:00
Alex Forencich
545eca653c Fix kernel module coding style 2021-10-22 14:36:41 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
e0167eedd8 Add AXI DMA interface modules and testbenches 2021-10-20 13:04:17 -07:00
Alex Forencich
b7e8ca1311 Fix kernel module coding style 2021-10-13 16:51:32 -07:00
Alex Forencich
8c5364e65a Update readme 2021-10-03 12:39:15 -07:00
Alex Forencich
cb6b15cae0 Reset error signal monitor 2021-10-03 12:17:57 -07:00
Alex Forencich
c41f0a823a Prevent latch inference 2021-10-03 11:55:27 -07:00
Alex Forencich
b2e34cd12a Byte count only needs 3 bits for single DWORD operations 2021-10-03 11:53:24 -07:00
Alex Forencich
ebac1a8be6 Derive length from op_read 2021-10-03 11:51:22 -07:00
Alex Forencich
04a80a4d35 Rework FIFO implementation for pcie_axil_master_minimal 2021-10-03 11:48:47 -07:00
Alex Forencich
85b8231abf Add IO operations to bad ops test for pcie_axil_master_minimal 2021-10-03 11:47:45 -07:00
Alex Forencich
bb74bdf2f7 Update pcie_axil_master module to support arbitrary memory operations 2021-10-03 11:46:55 -07:00
Alex Forencich
eea6b66f3f Add PCIe AXI master modules and testbenches 2021-10-02 00:59:18 -07:00
Alex Forencich
824e9fc758 Resize registers 2021-10-02 00:46:21 -07:00
Alex Forencich
75905778bc Use DRIVER_NAME define 2021-10-01 23:44:50 -07:00
Alex Forencich
437c69abc4 Call remove from shutdown 2021-10-01 18:25:31 -07:00
Alex Forencich
93aed3ede9 Remove UltraScale specific counters 2021-10-01 18:25:12 -07:00
Alex Forencich
4b59bad937 Print more PCIe information 2021-10-01 17:38:58 -07:00
Alex Forencich
cb52a82498 Remove MODULE_SUPPORTED_DEVICE, which was never implemented and was removed in kernel version 5.12 2021-10-01 17:35:43 -07:00
Alex Forencich
aee1431e74 Remove irrelevant address computation 2021-10-01 15:56:51 -07:00
Alex Forencich
d97ac3105f Convert VCU118 to x16 2021-10-01 15:56:28 -07:00
Alex Forencich
618fdff0b8 Convert ADM_PCIE_9V3 to x16 2021-10-01 15:21:10 -07:00
Alex Forencich
adeb2c6b1c Fix alignment 2021-10-01 13:50:30 -07:00
Alex Forencich
d0705fea9b Minor optimizations to completion TLP size computation logic 2021-10-01 13:00:22 -07:00
Alex Forencich
a7b669e22f Update makefiles 2021-10-01 02:39:15 -07:00
Alex Forencich
c044898ec4 One AXI read burst per completion TLP 2021-10-01 00:20:29 -07:00
Alex Forencich
2984b5b09d Copy pcie_axil_master as pcie_axil_master_minimal 2021-09-30 22:38:28 -07:00
Alex Forencich
f2f19f7174 Update terminology, use byte_lanes instead of byte_width 2021-09-25 22:52:19 -07:00
Alex Forencich
bc8715decc Hold read completions until pending writes complete 2021-09-25 00:46:55 -07:00
Alex Forencich
f25cfa0982 Update tox configuration 2021-09-13 13:00:03 -07:00
Alex Forencich
b131b2ebbf Rework DMA desc status demux to fix X issue at t=0 2021-09-09 00:58:48 -07:00
Alex Forencich
f566df2c66 Add TLP mux and demux modules 2021-09-08 10:04:38 -07:00
Alex Forencich
1321e8e41a Refactor check 2021-09-05 15:30:37 -07:00
Alex Forencich
8a6abc51ed Add statistics outputs to DMA interface 2021-09-05 15:29:56 -07:00
Alex Forencich
6af4461705 Fix length register widths and max value handling 2021-08-20 16:09:58 -07:00
Alex Forencich
0563eb4727 Check MSBs 2021-08-20 14:12:26 -07:00
Alex Forencich
85391d2b9b Compare all fields 2021-08-20 14:10:03 -07:00
Alex Forencich
943731d624 Use new modules in dma_if_mux modules 2021-08-16 18:04:38 -07:00
Alex Forencich
292f73f43d Add DMA RAM demux modules 2021-08-16 18:03:38 -07:00
Alex Forencich
1342e31976 Add DMA IF descriptor mux module 2021-08-16 18:03:22 -07:00
Alex Forencich
14c84088ee Reorganize driver code 2021-08-13 14:22:32 -07:00
Alex Forencich
7810b3c99e Connect RQ sequence number ports in pcie_us_if testbench 2021-08-11 19:53:28 -07:00
Alex Forencich
7fed6876a3 Init seq to 0 2021-08-11 19:52:47 -07:00
Alex Forencich
ac96ae97d3 Add flow control signals to pcie_us_if 2021-08-11 19:37:51 -07:00