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Author SHA1 Message Date
Alex Forencich
26fdddb3ae Update Alveo U250 designs 2021-09-11 01:27:23 -07:00
Alex Forencich
ec89492d24 Fix control register addressing bug 2021-09-11 00:49:48 -07:00
Alex Forencich
ed418f101a Update Alveo U200 designs 2021-09-10 23:40:53 -07:00
Alex Forencich
9b1188860b Update Alveo U50 designs 2021-09-10 19:07:55 -07:00
Alex Forencich
079ad5ec37 Add pblock for 10G MACs 2021-09-10 18:52:46 -07:00
Alex Forencich
9ee5463b92 Remove blank line 2021-09-10 18:52:22 -07:00
Alex Forencich
6a44a59b2c Move LED assignments 2021-09-10 10:53:41 -07:00
Alex Forencich
ada43236d9 Fix alignment 2021-09-09 23:17:52 -07:00
Alex Forencich
c56f6d717b Fix IDs 2021-09-09 22:05:27 -07:00
Alex Forencich
c92dbfe7ed Update file lists 2021-09-09 21:52:16 -07:00
Alex Forencich
fcf4bc007f Update Alveo U280 designs 2021-09-09 18:09:08 -07:00
Alex Forencich
2442ff65c5 Support application and RAM bars 2021-09-09 17:50:44 -07:00
Alex Forencich
d0976f193b Use correct type 2021-09-09 17:49:11 -07:00
Alex Forencich
d24c53a2ad Add application section 2021-09-09 16:01:26 -07:00
Alex Forencich
371717b854 Add block names 2021-09-09 14:12:41 -07:00
Alex Forencich
b097aa5c9e merged changes in pcie 2021-09-09 01:00:10 -07:00
Alex Forencich
b131b2ebbf Rework DMA desc status demux to fix X issue at t=0 2021-09-09 00:58:48 -07:00
Alex Forencich
97e3daa36c Extract information from design instead of env vars 2021-09-08 16:44:58 -07:00
Alex Forencich
c920272e84 Use interface address widths directly instead of BAR size parameters 2021-09-08 14:51:18 -07:00
Alex Forencich
3cbb4a9506 merged changes in pcie 2021-09-08 10:05:40 -07:00
Alex Forencich
f566df2c66 Add TLP mux and demux modules 2021-09-08 10:04:38 -07:00
Alex Forencich
cef144e376 Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters 2021-09-08 00:18:11 -07:00
Alex Forencich
c00a53155d Fix alignment 2021-09-07 01:38:09 -07:00
Alex Forencich
bdd2312ecc More descriptive parameter and signal names for AXI lite control connections 2021-09-07 01:35:15 -07:00
Alex Forencich
8cf16c182b More descriptive parameter names (SYNC instead of INT) 2021-09-07 01:29:35 -07:00
Alex Forencich
15dec9458a Add statistics counter subsystem 2021-09-05 23:03:22 -07:00
Alex Forencich
9ccd43d470 Add statistics collection modules 2021-09-05 18:28:37 -07:00
Alex Forencich
65178395ed merged changes in pcie 2021-09-05 15:43:16 -07:00
Alex Forencich
1321e8e41a Refactor check 2021-09-05 15:30:37 -07:00
Alex Forencich
8a6abc51ed Add statistics outputs to DMA interface 2021-09-05 15:29:56 -07:00
Alex Forencich
5d760851ac Limit queue manager pipelines to a single AXI lite operation 2021-09-05 12:46:56 -07:00
Alex Forencich
ef00d5ccfd Add parameters for FIFO output pipeline register depth 2021-09-02 14:45:18 -07:00
Alex Forencich
f3eeb653d1 Fix test 2021-09-02 00:00:37 -07:00
Alex Forencich
600001b894 Update placement constraints 2021-09-01 16:10:39 -07:00
Alex Forencich
34ae6a9513 merged changes in eth 2021-09-01 16:10:05 -07:00
Alex Forencich
c44e447db5 Transfer PTP information in tuser 2021-09-01 15:56:00 -07:00
Alex Forencich
b6f792cc10 merged changes in axis 2021-09-01 15:54:12 -07:00
Alex Forencich
6c234260b2 Fix assignment type 2021-09-01 15:53:15 -07:00
Alex Forencich
de869347cd Register interrupt signal 2021-09-01 13:14:02 -07:00
Alex Forencich
df9523011c Normalize instance names 2021-09-01 02:14:53 -07:00
Alex Forencich
09a10fc3ca Fix MAC clock period parameters 2021-09-01 02:06:25 -07:00
Alex Forencich
b630fdaeb0 Fix QSFP mapping comments 2021-09-01 02:01:14 -07:00
Alex Forencich
9295184e19 Fix signal width parametrization 2021-09-01 01:59:42 -07:00
Alex Forencich
fc835e0ab6 Use TX PTP CDC for both RX and TX due to synchronous clocking 2021-08-31 23:38:24 -07:00
Alex Forencich
82d0770daf Remove unused constraints file 2021-08-31 23:33:00 -07:00
Alex Forencich
c3d498101b Clarify widths 2021-08-31 23:32:42 -07:00
Alex Forencich
37a558e4f6 Add pipeline FIFOs 2021-08-31 22:30:45 -07:00
Alex Forencich
1fc991fc05 Convert fb2CG designs to use common core modules 2021-08-31 21:33:49 -07:00
Alex Forencich
915a915d6e Enable PCIe flow control in core tests 2021-08-31 20:38:08 -07:00
Alex Forencich
bd3fa6abfd Update vivado.mk 2021-08-31 20:03:33 -07:00