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Author SHA1 Message Date
Alex Forencich
a4bc99bb1b Fix parameters 2019-09-05 05:23:20 -07:00
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62cbaa1bd1 Remove extraneous code 2019-07-25 15:44:37 -07:00
Alex Forencich
8547057f32 Fix to enable M_COUNT of 1 2019-07-24 18:18:44 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
d694a67190 Update priority encoder 2019-07-24 14:22:47 -07:00
Alex Forencich
23a14dc5df Update readme 2019-07-09 00:18:58 -07:00
Alex Forencich
21dbe318b4 Add AXI lite clock domain crossing module, testbench, and timing constraints 2019-07-09 00:18:27 -07:00
Alex Forencich
36523dd7cc Fix typo 2019-07-08 17:57:47 -07:00
Alex Forencich
f924f75b70 Use computed word size 2019-07-08 17:57:30 -07:00
Alex Forencich
7591cb4d1c Update readme 2019-07-08 17:53:39 -07:00
Alex Forencich
ed344f352f Add AXI to AXI lite adapter modules and testbenches 2019-07-08 17:51:12 -07:00
Alex Forencich
f5830b6407 Backpressure updates 2019-07-08 17:34:09 -07:00
Alex Forencich
abcb20612e Remove redundant code 2019-07-08 00:28:27 -07:00
Alex Forencich
1bd22f5208 Ensure rready clear when returning to idle 2019-07-05 23:29:39 -07:00
Alex Forencich
3f21db4584 bresp handling update 2019-07-04 14:23:37 -07:00
Alex Forencich
7fd0f79f81 Remove extraneous parameter 2019-06-26 12:26:55 -07:00
Alex Forencich
94a3be6e1d Fix possible backpressure issue 2019-06-22 12:47:52 -07:00
Alex Forencich
f6acefbf94 Simplify logic 2019-06-22 01:51:06 -07:00
Alex Forencich
ebbaea908b Add strb_offset_mask_reg 2019-06-22 00:13:11 -07:00
Alex Forencich
b1edaf1ae4 Optimize check 2019-06-22 00:05:15 -07:00
Alex Forencich
6ed937d521 Add zero offset reg 2019-06-21 20:42:20 -07:00
Alex Forencich
967aa8c2f3 Mask instead of barrel shift 2019-06-21 20:38:09 -07:00
Alex Forencich
435f0b8749 Timing optimization of wstrb 2019-06-21 12:04:58 -07:00
Alex Forencich
834d6a4b2d Improve timing for unaligned operations (shift_axis_extra_cycle) 2019-06-15 21:27:41 -07:00
Alex Forencich
b0cda50aba Fix AXIL interconnect read bug 2019-06-12 17:57:39 -07:00
Alex Forencich
5581a76c0b Use correct clocks 2019-05-14 18:57:01 -07:00
Alex Forencich
7b33dde069 Fix state encoding 2019-05-06 17:37:09 -07:00
Alex Forencich
664949b7d6 Cleanup 2019-04-12 12:39:35 -07:00
Alex Forencich
685353c6e4 Rework AXI memory interfaces 2019-04-06 23:16:21 -07:00
Alex Forencich
a60e1f726f Fix use before define 2019-03-18 14:02:10 -07:00
Alex Forencich
f128190130 Ensure transfer is terminated at the end of the input frame 2019-03-13 14:48:05 -07:00
Alex Forencich
101be9fa2c Fix use before define 2019-03-12 13:15:11 -07:00
Alex Forencich
620526d581 Also match transfers by region 2019-03-12 12:58:56 -07:00
Alex Forencich
e71a62e6a1 Fix backpressure issue 2019-03-07 17:45:25 -08:00
Alex Forencich
4d628c9171 Fix thread matching 2019-03-06 13:40:29 -08:00
Alex Forencich
724f18113c Fix bug 2019-03-05 22:20:44 -08:00
Alex Forencich
e9cd97f0b4 Pass through more signals in AXI RAM interfaces 2019-02-26 01:25:03 -08:00
Alex Forencich
8478c5d076 Incorrect signals 2019-02-25 20:37:55 -08:00
Alex Forencich
a501df6965 Update readme 2019-02-25 18:56:39 -08:00
Alex Forencich
7b713199ad Add AXI nonblocking crossbar interconnect module and testbench 2019-02-25 18:37:46 -08:00
Alex Forencich
365e063bc7 Add AXI DMA and CDMA descriptor mux modules 2019-02-25 15:44:10 -08:00
Alex Forencich
04dd6a34d7 Fix combinatorial loop 2019-02-20 18:48:27 -08:00
Alex Forencich
7654d874ae Fix out of range access due to off by one error 2019-02-11 19:30:57 -08:00
Alex Forencich
57dd292ae9 Add AXI RAM interface modules, AXI dual port RAM module, and testbench 2019-02-01 18:22:03 -08:00
Alex Forencich
199a5544ca Use correct wait 2019-02-01 17:28:22 -08:00
Alex Forencich
787f198970 Add AXI lite dual-port RAM module and testbench 2019-01-17 17:48:23 -08:00
Alex Forencich
b1f40411ad Remove unnecessary reset 2019-01-17 17:09:55 -08:00
Alex Forencich
818fac5daa Update signal names 2019-01-16 19:37:15 -08:00
Alex Forencich
523bf689d8 Add optional output pipeline register to AXI lite RAM 2019-01-09 00:25:40 -08:00