Alex Forencich
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a2f07db39f
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Remove redundant abort signal connection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-14 14:55:01 -07:00 |
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Alex Forencich
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60dd672f6d
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Move pause signal connection to improve timing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-14 14:54:27 -07:00 |
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Alex Forencich
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1dfdd8b0e3
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Timing optimization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-31 17:24:03 -07:00 |
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Alex Forencich
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b1b82a3f2b
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Add pause inputs to TLP mux modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-29 17:16:05 -07:00 |
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Alex Forencich
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cc1278f9d9
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Update PCIe TLP mux to handle multiple segments
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-02 23:40:35 -07:00 |
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Alex Forencich
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df32016724
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Add sequence number ports to TLP mux and demux modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-05 17:34:12 -07:00 |
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Alex Forencich
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70dc92c24e
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Rework TLP interface parametrization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-05 13:27:04 -07:00 |
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Alex Forencich
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234c318ea1
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Pipeline arbitration delay in muxes
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-15 19:25:55 -07:00 |
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Alex Forencich
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ae1f4a9a22
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Rewrite early ready condition
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-15 19:25:30 -07:00 |
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Alex Forencich
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8cdb780ee3
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Rewrite resets
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-15 17:57:26 -07:00 |
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Alex Forencich
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90959b8795
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Add default_nettype none and resetall directives
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2021-10-20 17:49:30 -07:00 |
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Alex Forencich
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f566df2c66
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Add TLP mux and demux modules
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2021-09-08 10:04:38 -07:00 |
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