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Author	SHA1	Message	Date
Alex Forencich	ffd04d2bb0	Cleanup	2020-07-28 19:00:33 -07:00
Alex Forencich	495178e1dc	Fix mask	2020-07-28 18:30:52 -07:00
Alex Forencich	e4566dc545	merged changes in pcie	2020-07-28 16:00:31 -07:00
Alex Forencich	8045992eb6	Remove extraneous code	2020-07-27 22:29:04 -07:00
Alex Forencich	1f523f0bb4	Remove unused reg	2020-07-26 21:39:10 -07:00
Alex Forencich	dd97d2d749	Minor refactoring	2020-07-25 22:09:30 -07:00
Alex Forencich	dc48d86b99	Improve BAR initialization	2020-07-24 22:54:55 -07:00
Alex Forencich	d449be8fc5	Convert to 64 bit BARs	2020-07-24 16:54:57 -07:00
Alex Forencich	65fd5ef947	Fix AU50 XDC file	2020-07-23 22:36:00 -07:00
Alex Forencich	cdc14769c3	Update readme	2020-07-17 01:45:25 -07:00
Alex Forencich	2a23be508a	Add 100G mqnic design for Alveo U50	2020-07-17 01:44:59 -07:00
Alex Forencich	deb895ff05	Add 10G mqnic design for Alveo U50	2020-07-17 01:44:28 -07:00
Alex Forencich	18f56fcb16	Remove extraneous signals	2020-07-17 00:57:47 -07:00
Alex Forencich	56dbcb8274	Add AU50 AXI example design	2020-07-17 00:04:13 -07:00
Alex Forencich	837a390567	Fix VCU118 CMAC reference clocks	2020-07-14 10:47:18 -07:00
Alex Forencich	20eac98bde	Clean up	2020-07-14 00:33:12 -07:00
Alex Forencich	d3a1c903d3	XDC clean up	2020-07-13 23:58:45 -07:00
Alex Forencich	e230fecb23	XDC clean up	2020-07-13 23:58:39 -07:00
Alex Forencich	35ec697a6f	Update readme	2020-07-13 13:41:33 -07:00
Alex Forencich	5dbb771958	Add AU280 AXI example design	2020-07-12 11:42:48 -07:00
Alex Forencich	fe729cdd86	Update readme	2020-07-12 11:34:31 -07:00
Alex Forencich	9b7fa688d5	Add 100G mqnic design for Alveo U280	2020-07-12 11:33:28 -07:00
Alex Forencich	6433275139	Add 10G mqnic design for Alveo U280	2020-07-12 11:33:18 -07:00
Alex Forencich	2d4c7925f0	Add Alveo board IDs	2020-07-11 23:07:50 -07:00
Alex Forencich	f99736d4f5	Convert to TCL IP	2020-07-11 20:07:13 -07:00
Alex Forencich	5dd5f8bb3e	merged changes in pcie	2020-07-10 19:46:48 -07:00
Alex Forencich	7c10036183	merged changes in eth	2020-07-10 19:46:43 -07:00
Alex Forencich	0ff6282ed6	merged changes in axi	2020-07-10 19:46:37 -07:00
Alex Forencich	ce41b4c5ea	Update readme	2020-07-10 16:07:31 -07:00
Alex Forencich	3898cf21ed	Add DE2-115 example design	2020-07-10 15:38:43 -07:00
Alex Forencich	3b06f86dcf	Add C10LP example design	2020-07-10 15:32:39 -07:00
Alex Forencich	59a51b4a9f	Add SDC constraints for Quartus	2020-07-10 14:14:02 -07:00
Alex Forencich	65cb3cb441	merged changes in axis	2020-07-10 14:04:52 -07:00
Alex Forencich	71bd4a1811	Add SDC constraints for Quartus	2020-07-10 14:02:08 -07:00
Alex Forencich	ebae4e436d	Update AXI simulation model	2020-07-02 21:28:35 -07:00
Alex Forencich	281e1a2156	Convert to TCL IP	2020-07-01 23:53:58 -07:00
Alex Forencich	a27c04a949	Convert to TCL IP	2020-07-01 19:43:26 -07:00
Alex Forencich	839ea23ac4	Fix arb mux header backpressure	2020-05-17 21:50:24 -07:00
Alex Forencich	d6ad22d435	Add DMA block diagram	2020-05-07 12:36:37 -07:00
Alex Forencich	b31c390d3e	Assume tkeep[0] always high	2020-05-05 16:17:51 -07:00
Alex Forencich	4d4c7df5b6	Parametrize eth_axis_fcs	2020-05-05 16:13:02 -07:00
Alex Forencich	7d561c713f	Update userspace utils	2020-05-01 21:55:50 -07:00
Alex Forencich	6d26adf916	Add MTU registers to driver	2020-05-01 21:54:44 -07:00
Alex Forencich	4e958096b2	Update driver model to set MTU registers	2020-05-01 19:19:56 -07:00
Alex Forencich	ae775a9386	Rewrite RX buffer management	2020-05-01 19:00:58 -07:00
Alex Forencich	8b535e54ac	Add MTU registers	2020-05-01 18:55:01 -07:00
Alex Forencich	ca0cbf4d93	Update parameters	2020-05-01 17:22:21 -07:00
Alex Forencich	1f76606667	Move TDMA registers	2020-05-01 16:55:57 -07:00
Alex Forencich	ded213460d	Rewrite TX buffer management	2020-05-01 14:29:52 -07:00
Alex Forencich	1c7b7937e5	Limit in-flight descriptor requests in TX engine	2020-04-30 23:37:41 -07:00