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  • 618e8566c9
         Merge e104aaa36c9d5ea83ba23ecfe92ac348ad574615 into 1ca0151b97af85aa5dd306d74b6bcec65904d2ce muvarov 2024-12-05 10:29:57 +00:00
  • e104aaa36c mqnic: update ethtool rxfh to recent kernel Maxim Uvarov 2024-12-05 19:34:11 +03:00
  • 9f3c8ac0f7 mqnic: fix strlcpy Maxim Uvarov 2024-12-05 19:12:55 +03:00
  • 36ebbce7a2
         Merge 631131e33ecfd15f93fb5b9abcb205226c2011f8 into 1ca0151b97af85aa5dd306d74b6bcec65904d2ce Vladislav Borshch 2024-11-15 10:53:10 +07:00
  • 631131e33e fix possible bug with parallel build utils Vladislav Borshch 2024-11-15 10:48:36 +07:00
  • 261f80dfe7
         Merge 6d56d7f21251e75dfcfb3a36eabb806fb19431ef into 1ca0151b97af85aa5dd306d74b6bcec65904d2ce Vladislav Borshch 2024-09-17 14:42:03 +07:00
  • 6d56d7f212 fix: increase hardware MTU size due to cut frames in case of vlan tagging Vladislav Borshch 2024-09-17 14:38:03 +07:00
  • ed2e0fe798
         Merge 458b93a8303ffc956c89198c96bf42d4f91bce83 into 1ca0151b97af85aa5dd306d74b6bcec65904d2ce Vladislav Borshch 2024-07-05 08:24:14 +00:00
  • 458b93a830 mqnic: no pci build. fix issue with incorrect pci_irq function masking for systems with mqnic-to-ps connection Vladislav Borshch 2024-07-05 15:23:03 +07:00
  • 0e143d0e49
         Merge 66b038c8a9eaa335733994632274710428db062f into 1ca0151b97af85aa5dd306d74b6bcec65904d2ce Yuji YAMADA 2024-05-22 11:55:25 +00:00
  • 66b038c8a9 Fix: voltage problem. offnaria 2024-05-22 20:18:57 +09:00
  • 883ea6ccdf Update fpga.xdc: bind fan_control to A12. offnaria 2024-05-22 19:53:55 +09:00
  • f590d0081e Update fpga.v: make external output port for fan controlling. offnaria 2024-05-22 19:32:48 +09:00
  • 9ee9475d36 Update zynq_ps.tcl: make external pin for fan controlling. offnaria 2024-05-22 19:26:20 +09:00
  • 0aa34592d9 04_30 liuqiliqi 2024-04-30 07:29:24 +00:00
  • f3b565960e
         0418 liuqiliqi 2024-04-29 22:16:26 +08:00
  • d721c1638f
         0418 liuqiliqi 2024-04-29 21:40:59 +08:00
  • dfdae78e6b
         0418 liuqiliqi 2024-04-29 21:19:53 +08:00
  • 60ce893396
         Add files via upload liuqiliqi 2024-04-29 20:33:49 +08:00
  • b375274bf0
         0419 liuqiliqi 2024-04-29 20:04:44 +08:00
  • 14e4bb14af
         Add files via upload liuqiliqi 2024-04-29 19:45:51 +08:00
  • 3a0a9fb977 manually free sender buffer Yufeng Ying 2024-04-23 20:22:07 +08:00
  • 521f9c1790 fix waiting logic Yufeng Ying 2024-04-23 18:27:57 +08:00
  • 2ddff99902 send new packet after NIC processed prev one Yufeng Ying 2024-04-22 18:38:59 +08:00
  • 485516b33b manually DMA map/unmap buffer Yufeng Ying 2024-04-17 18:11:51 +08:00
  • 2d56f101a1 cleanup dma map/unmap part Yufeng Ying 2024-04-17 17:27:06 +08:00
  • 7810941f82 enable multi-txq support Yufeng Ying 2024-04-16 23:31:06 +08:00
  • 32be7e5b21 track multiple ring in mqnic_dev Yufeng Ying 2024-04-16 22:59:59 +08:00
  • 48d9a5460c refact: change CLI command, use packets file to specify packets to send Yufeng Ying 2024-04-16 05:06:03 +08:00
  • ecbcdf3ef7 echo cli args && fix buffer overflow Yufeng Ying 2024-04-09 21:33:25 +08:00
  • d8a8825d40 fix arg parse bug Yufeng Ying 2024-04-09 21:07:49 +08:00
  • 42abf39ec1 add lock to ioctl to prevent parallel call Yufeng Ying 2024-04-09 20:09:51 +08:00
  • e753b8a3d6 fix: check tx_ring full before write WQE Yufeng Ying 2024-04-09 19:26:36 +08:00
  • e03d1ee13e add single QP benchmark mode Yufeng Ying 2024-04-09 16:38:48 +08:00
  • 113ddd3d2a opt err message Yufeng Ying 2024-04-02 12:20:05 +08:00
  • 923bf26ce4 fix receiver display bug Yufeng Ying 2024-04-02 12:13:42 +08:00
  • a053308742 fill udp dst port Yufeng Ying 2024-04-01 14:46:13 +08:00
  • 23f60da4b2 accept remote addr at sender side Yufeng Ying 2024-04-01 14:31:48 +08:00
  • ba0dfa5e28 print dma addr at console Yufeng Ying 2024-03-29 14:18:06 +08:00
  • 3e9b39d9f2 impl receiver mem scan Yufeng Ying 2024-03-29 14:03:29 +08:00
  • 50951dc030 add more logs, fix lang server warning Yufeng Ying 2024-03-29 11:11:58 +08:00
  • 26650bbe0f interrupt kernel tx Yufeng Ying 2024-03-27 17:29:56 +08:00
  • dcb78de6d7 fix buffer len incorrectly aligned to PAGE_SIZE Yufeng Ying 2024-03-26 11:17:20 +08:00
  • 903f79e909 fix incorrect page num when buffer contain half page Yufeng Ying 2024-03-25 20:44:22 +08:00
  • 5792e12934 fix README Yufeng Ying 2024-03-25 17:52:51 +08:00
  • b3779eeca8 add Readme Yufeng Ying 2024-03-25 17:45:06 +08:00
  • 7fe731014c add userspace packet sender Yufeng Ying 2024-03-25 17:24:55 +08:00
  • df44dc2a1a add v3 test driver Yufeng Ying 2024-03-25 17:03:02 +08:00
  • 3c6652785e update dpdk tools Huangxy-Minel 2024-01-15 16:05:41 +08:00
  • 3d03f074e1 update bit files Huangxy-Minel 2023-12-28 16:48:28 +08:00
  • 0d7b74dfdd
         Merge 8666f4ee97da238a74a3289a36ff50ad47b45c28 into 1ca0151b97af85aa5dd306d74b6bcec65904d2ce oskar-mle 2023-12-20 13:24:20 +00:00
  • 8666f4ee97 fpga/app/custom_port_demo/utils/zcu102_demo.sh: add simple script to showcase demo app functionality Oskar Szakinnis 2023-11-17 17:22:43 +01:00
  • 7c5440058f fpga/mqnic/ZCU102/fpga/fpga_app_custom_port_demo/: add build configuration for ZCU102 custom port demo app Oskar Szakinnis 2023-11-17 17:21:58 +01:00
  • 98374a6165 fpga/mqnic/ZCU102/fpga/rtl/: add custom port demo app implementation for ZCU102 Oskar Szakinnis 2023-11-17 17:20:45 +01:00
  • 5bf7f8bbae create copies of ZCU102 design files (fpga build configuration folder, fpga_core.v, fpga.v) for as base for board-specific custom port demo design Oskar Szakinnis 2023-11-27 15:44:48 +01:00
  • 8235ec7d74 fpga/app/custom_port_demo/rtl/: add platform-agnostic custom port demo app base implementation Oskar Szakinnis 2023-11-17 17:14:21 +01:00
  • b64a582e5c update dpdk tool Huangxy-Minel 2023-12-18 21:00:43 +08:00
  • c1f1bb85f2 update corundum base & update ainic v1 src Huangxy-Minel 2023-12-18 13:54:48 +08:00
  • 9e2f3cbb14 create copy of template app (only lib/ and rtl/) as base for custom port demo design Oskar Szakinnis 2023-11-27 15:37:06 +01:00
  • d1c7d02e2d fpga/app/template/rtl/: add template verilog headers for custom ports and parameters Oskar Szakinnis 2023-11-08 14:12:54 +01:00
  • 1903a8de6d fpga/common/rtl/, fpga/app/template/rtl/: add custom port and parameter macros to relevant source files Oskar Szakinnis 2023-11-08 11:58:56 +01:00
  • 1ca0151b97 merged changes in eth master Alex Forencich 2023-12-02 01:30:49 -08:00
  • dce0c92a57 Rework PHC to register shared adder outputs for improved timing performance Alex Forencich 2023-12-02 00:53:02 -08:00
  • dd97924714 Prevent stale data frim being used to sync leaf clock Alex Forencich 2023-12-01 22:05:53 -08:00
  • f0c47db509 Improve tolerance of sample point synchronization Alex Forencich 2023-12-01 22:03:14 -08:00
  • a2294c56a5 Rewrite gain scheduling Alex Forencich 2023-12-01 22:02:40 -08:00
  • 89ee44d410 Add test for PCIe spread spectrum clocking Alex Forencich 2023-12-01 22:02:09 -08:00
  • 65de3818f0 code sync Huangxy-Minel 2023-12-02 13:54:35 +08:00
  • 5c12f1bd91 code sync Huangxy-Minel 2023-12-02 13:52:01 +08:00
  • 71fd895f1a code sync Huangxy-Minel 2023-12-02 13:29:54 +08:00
  • 36cf9c9b06 Remove unnecessary shadow valid registers Alex Forencich 2023-12-01 14:03:55 -08:00
  • be0d9b7b88 Improve handling of instance name mangling Alex Forencich 2023-12-01 13:37:25 -08:00
  • 1099e44304 code sync and add ai nic sub proj Huangxy-Minel 2023-12-01 15:14:45 +08:00
  • 5560fa2b32 Fix timestamp capture/sync logic Alex Forencich 2023-11-30 14:05:16 -08:00
  • 16cd84123d Add user_sma_clk pins to VCU108 and VCU118 constraints files Alex Forencich 2023-11-29 13:58:22 -08:00
  • bf3636ff15 fpga/mqnic: Add user_sma_clk pins to VCU108 and VCU118 constraints files Alex Forencich 2023-11-29 00:37:51 -08:00
  • ba55a3c1ed fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter Alex Forencich 2023-11-28 18:57:10 -08:00
  • a839ecf4cc fpga/mqnic/VCU118: Fix VCU118 refclk Alex Forencich 2023-11-28 00:20:31 -08:00
  • 1f3b739bb6 fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control Alex Forencich 2023-11-27 17:25:42 -08:00
  • 51b9eb251b fpga/mqnic/ZCU106: Add notes for boot mode selection on ZCU106 Alex Forencich 2023-11-23 00:51:38 -08:00
  • baf3279982 fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing Alex Forencich 2023-11-23 00:49:07 -08:00
  • d9c856b877 fpga/common: Update clock info register block timing constraints to handle clocks from OOC cores that are not defined during synthesis Alex Forencich 2023-11-23 00:41:21 -08:00
  • 2e8e24f446 fpga/mqnic/Alveo: Fix Alveo flash format register Alex Forencich 2023-11-20 00:18:39 -08:00
  • 179fd275b5 Update device lists Alex Forencich 2023-11-19 21:16:28 -08:00
  • c61bbd6f0d fpga/mqnic: Clean up IO constraints for Intel devices Alex Forencich 2023-11-19 21:15:05 -08:00
  • b4febeb78e fpga/mqnic: Add missing PTP clock connections Alex Forencich 2023-11-19 19:52:09 -08:00
  • 98e76987e5 modules/mqnic: Set port phys_index Alex Forencich 2023-11-19 19:51:52 -08:00
  • e9ea91b5ec fpga/mqnic: Set data bus width correctly for 25G E-Tile MACs Alex Forencich 2023-11-19 19:51:32 -08:00
  • a7753da72e Add support for BittWare IA-420F Alex Forencich 2023-11-19 19:51:12 -08:00
  • 67e0e07c43 fpga/mqnic/DK_DEV_AGF014EA: set port group size based on selected MAC rate Alex Forencich 2023-11-19 19:50:29 -08:00
  • c48735216c fpga/mqnic/Alveo: Rework AU200 clocking Alex Forencich 2023-11-19 19:50:07 -08:00
  • 534cd3735f fpga/mqnic/Alveo: Rework AU55 clocking Alex Forencich 2023-11-15 11:28:35 -08:00
  • cccd983975 fpga/mqnic/Alveo: Rework AU280 clocking Alex Forencich 2023-11-15 11:28:14 -08:00
  • 152c96dc00 fpga/mqnic/Alveo: Rework AU50 clocking Alex Forencich 2023-11-15 11:25:45 -08:00
  • 0c35085714 fpga/common/rtl: Update scheduler block parameters and PTP connections Alex Forencich 2023-11-14 21:51:15 -08:00
  • 614b33a205 fpga/mqnic/DK_DEV_1SDX_P_A: Fix MAC timing constraints for DK-DEV-1SDX-P-A Alex Forencich 2023-11-14 18:19:29 -08:00
  • 55c5ea335f fpga/mqnic/DK_DEV_AGF014EA: Fix MAC timing constraints for DK-DEV-AGF014EA Alex Forencich 2023-11-14 18:13:25 -08:00
  • 184b7242e9 fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex Alex Forencich 2023-11-14 18:11:59 -08:00
  • 545fb3ca22 fpga/mqnic/XUPP3R: Add missing TCL script for XUSP3S PCIe IP core Alex Forencich 2023-11-14 17:54:03 -08:00
  • 3f7a4cee27 fpga/mqnic: Fix datapath width parameter for 25G Alex Forencich 2023-11-13 21:39:42 -08:00