// SPDX-License-Identifier: BSD-2-Clause-Views /* * Copyright (c) 2022-2023 The Regents of the University of California */ #ifndef GTYE3_REGS_H #define GTYE3_REGS_H #include #ifndef BIT_MASK #define BIT_MASK(h, l) \ ((~0UL << ((l) & (sizeof(1UL)*CHAR_BIT-1))) & \ (~0UL >> (((-(h)-1) & (sizeof(1UL)*CHAR_BIT-1))))) #endif // common registers #define GTYE3_COM_QPLL0_CFG0_ADDR 0x0008 #define GTYE3_COM_QPLL0_CFG0_MSB 15 #define GTYE3_COM_QPLL0_CFG0_LSB 0 #define GTYE3_COM_QPLL0_CFG0_MASK BIT_MASK(GTYE3_COM_QPLL0_CFG0_MSB, GTYE3_COM_QPLL0_CFG0_LSB) #define GTYE3_COM_COMMON_CFG0_ADDR 0x0009 #define GTYE3_COM_COMMON_CFG0_MSB 15 #define GTYE3_COM_COMMON_CFG0_LSB 0 #define GTYE3_COM_COMMON_CFG0_MASK BIT_MASK(GTYE3_COM_COMMON_CFG0_MSB, GTYE3_COM_COMMON_CFG0_LSB) #define GTYE3_COM_RSVD_ATTR0_ADDR 0x000B #define GTYE3_COM_RSVD_ATTR0_MSB 15 #define GTYE3_COM_RSVD_ATTR0_LSB 0 #define GTYE3_COM_RSVD_ATTR0_MASK BIT_MASK(GTYE3_COM_RSVD_ATTR0_MSB, GTYE3_COM_RSVD_ATTR0_LSB) #define GTYE3_COM_PPF0_CFG_ADDR 0x000D #define GTYE3_COM_PPF0_CFG_MSB 15 #define GTYE3_COM_PPF0_CFG_LSB 0 #define GTYE3_COM_PPF0_CFG_MASK BIT_MASK(GTYE3_COM_PPF0_CFG_MSB, GTYE3_COM_PPF0_CFG_LSB) #define GTYE3_COM_QPLL0CLKOUT_RATE_ADDR 0x000E #define GTYE3_COM_QPLL0CLKOUT_RATE_MSB 0 #define GTYE3_COM_QPLL0CLKOUT_RATE_LSB 0 #define GTYE3_COM_QPLL0CLKOUT_RATE_MASK BIT_MASK(GTYE3_COM_QPLL0CLKOUT_RATE_MSB, GTYE3_COM_QPLL0CLKOUT_RATE_LSB) #define GTYE3_COM_QPLL0CLKOUT_RATE_HALF 0 #define GTYE3_COM_QPLL0CLKOUT_RATE_FULL 1 #define GTYE3_COM_QPLL0_CFG1_ADDR 0x0010 #define GTYE3_COM_QPLL0_CFG1_MSB 15 #define GTYE3_COM_QPLL0_CFG1_LSB 0 #define GTYE3_COM_QPLL0_CFG1_MASK BIT_MASK(GTYE3_COM_QPLL0_CFG1_MSB, GTYE3_COM_QPLL0_CFG1_LSB) #define GTYE3_COM_QPLL0_CFG2_ADDR 0x0011 #define GTYE3_COM_QPLL0_CFG2_MSB 15 #define GTYE3_COM_QPLL0_CFG2_LSB 0 #define GTYE3_COM_QPLL0_CFG2_MASK BIT_MASK(GTYE3_COM_QPLL0_CFG2_MSB, GTYE3_COM_QPLL0_CFG2_LSB) #define GTYE3_COM_QPLL0_LOCK_CFG_ADDR 0x0012 #define GTYE3_COM_QPLL0_LOCK_CFG_MSB 15 #define GTYE3_COM_QPLL0_LOCK_CFG_LSB 0 #define GTYE3_COM_QPLL0_LOCK_CFG_MASK BIT_MASK(GTYE3_COM_QPLL0_LOCK_CFG_MSB, GTYE3_COM_QPLL0_LOCK_CFG_LSB) #define GTYE3_COM_QPLL0_INIT_CFG0_ADDR 0x0013 #define GTYE3_COM_QPLL0_INIT_CFG0_MSB 15 #define GTYE3_COM_QPLL0_INIT_CFG0_LSB 0 #define GTYE3_COM_QPLL0_INIT_CFG0_MASK BIT_MASK(GTYE3_COM_QPLL0_INIT_CFG0_MSB, GTYE3_COM_QPLL0_INIT_CFG0_LSB) #define GTYE3_COM_QPLL0_INIT_CFG1_ADDR 0x0014 #define GTYE3_COM_QPLL0_INIT_CFG1_MSB 15 #define GTYE3_COM_QPLL0_INIT_CFG1_LSB 8 #define GTYE3_COM_QPLL0_INIT_CFG1_MASK BIT_MASK(GTYE3_COM_QPLL0_INIT_CFG1_MSB, GTYE3_COM_QPLL0_INIT_CFG1_LSB) #define GTYE3_COM_QPLL0_FBDIV_ADDR 0x0014 #define GTYE3_COM_QPLL0_FBDIV_MSB 7 #define GTYE3_COM_QPLL0_FBDIV_LSB 0 #define GTYE3_COM_QPLL0_FBDIV_MASK BIT_MASK(GTYE3_COM_QPLL0_FBDIV_MSB, GTYE3_COM_QPLL0_FBDIV_LSB) #define GTYE3_COM_QPLL0_CFG3_ADDR 0x0015 #define GTYE3_COM_QPLL0_CFG3_MSB 15 #define GTYE3_COM_QPLL0_CFG3_LSB 0 #define GTYE3_COM_QPLL0_CFG3_MASK BIT_MASK(GTYE3_COM_QPLL0_CFG3_MSB, GTYE3_COM_QPLL0_CFG3_LSB) #define GTYE3_COM_QPLL0_CP_ADDR 0x0016 #define GTYE3_COM_QPLL0_CP_MSB 9 #define GTYE3_COM_QPLL0_CP_LSB 0 #define GTYE3_COM_QPLL0_CP_MASK BIT_MASK(GTYE3_COM_QPLL0_CP_MSB, GTYE3_COM_QPLL0_CP_LSB) #define GTYE3_COM_QPLL0_REFCLK_DIV_ADDR 0x0018 #define GTYE3_COM_QPLL0_REFCLK_DIV_MSB 11 #define GTYE3_COM_QPLL0_REFCLK_DIV_LSB 7 #define GTYE3_COM_QPLL0_REFCLK_DIV_MASK BIT_MASK(GTYE3_COM_QPLL0_REFCLK_DIV_MSB, GTYE3_COM_QPLL0_REFCLK_DIV_LSB) #define GTYE3_COM_QPLL0_REFCLK_DIV_1 16 #define GTYE3_COM_QPLL0_REFCLK_DIV_2 0 #define GTYE3_COM_QPLL0_REFCLK_DIV_3 1 #define GTYE3_COM_QPLL0_REFCLK_DIV_4 2 #define GTYE3_COM_QPLL0_REFCLK_DIV_5 3 #define GTYE3_COM_QPLL0_REFCLK_DIV_6 5 #define GTYE3_COM_QPLL0_REFCLK_DIV_8 6 #define GTYE3_COM_QPLL0_REFCLK_DIV_10 7 #define GTYE3_COM_QPLL0_REFCLK_DIV_12 13 #define GTYE3_COM_QPLL0_REFCLK_DIV_16 14 #define GTYE3_COM_QPLL0_REFCLK_DIV_20 15 #define GTYE3_COM_QPLL0_IPS_REFCLK_SEL_ADDR 0x0018 #define GTYE3_COM_QPLL0_IPS_REFCLK_SEL_MSB 5 #define GTYE3_COM_QPLL0_IPS_REFCLK_SEL_LSB 3 #define GTYE3_COM_QPLL0_IPS_REFCLK_SEL_MASK BIT_MASK(GTYE3_COM_QPLL0_IPS_REFCLK_SEL_MSB, GTYE3_COM_QPLL0_IPS_REFCLK_SEL_LSB) #define GTYE3_COM_QPLL0_IPS_EN_ADDR 0x0018 #define GTYE3_COM_QPLL0_IPS_EN_MSB 0 #define GTYE3_COM_QPLL0_IPS_EN_LSB 0 #define GTYE3_COM_QPLL0_IPS_EN_MASK BIT_MASK(GTYE3_COM_QPLL0_IPS_EN_MSB, GTYE3_COM_QPLL0_IPS_EN_LSB) #define GTYE3_COM_QPLL0_LPF_ADDR 0x0019 #define GTYE3_COM_QPLL0_LPF_MSB 9 #define GTYE3_COM_QPLL0_LPF_LSB 0 #define GTYE3_COM_QPLL0_LPF_MASK BIT_MASK(GTYE3_COM_QPLL0_LPF_MSB, GTYE3_COM_QPLL0_LPF_LSB) #define GTYE3_COM_QPLL0_CFG1_G3_ADDR 0x001A #define GTYE3_COM_QPLL0_CFG1_G3_MSB 15 #define GTYE3_COM_QPLL0_CFG1_G3_LSB 0 #define GTYE3_COM_QPLL0_CFG1_G3_MASK BIT_MASK(GTYE3_COM_QPLL0_CFG1_G3_MSB, GTYE3_COM_QPLL0_CFG1_G3_LSB) #define GTYE3_COM_QPLL0_CFG2_G3_ADDR 0x001B #define GTYE3_COM_QPLL0_CFG2_G3_MSB 15 #define GTYE3_COM_QPLL0_CFG2_G3_LSB 0 #define GTYE3_COM_QPLL0_CFG2_G3_MASK BIT_MASK(GTYE3_COM_QPLL0_CFG2_G3_MSB, GTYE3_COM_QPLL0_CFG2_G3_LSB) #define GTYE3_COM_QPLL0_LPF_G3_ADDR 0x001C #define GTYE3_COM_QPLL0_LPF_G3_MSB 9 #define GTYE3_COM_QPLL0_LPF_G3_LSB 0 #define GTYE3_COM_QPLL0_LPF_G3_MASK BIT_MASK(GTYE3_COM_QPLL0_LPF_G3_MSB, GTYE3_COM_QPLL0_LPF_G3_LSB) #define GTYE3_COM_QPLL0_LOCK_CFG_G3_ADDR 0x001D #define GTYE3_COM_QPLL0_LOCK_CFG_G3_MSB 15 #define GTYE3_COM_QPLL0_LOCK_CFG_G3_LSB 0 #define GTYE3_COM_QPLL0_LOCK_CFG_G3_MASK BIT_MASK(GTYE3_COM_QPLL0_LOCK_CFG_G3_MSB, GTYE3_COM_QPLL0_LOCK_CFG_G3_LSB) #define GTYE3_COM_RSVD_ATTR1_ADDR 0x001E #define GTYE3_COM_RSVD_ATTR1_MSB 15 #define GTYE3_COM_RSVD_ATTR1_LSB 0 #define GTYE3_COM_RSVD_ATTR1_MASK BIT_MASK(GTYE3_COM_RSVD_ATTR1_MSB, GTYE3_COM_RSVD_ATTR1_LSB) #define GTYE3_COM_QPLL0_FBDIV_G3_ADDR 0x001F #define GTYE3_COM_QPLL0_FBDIV_G3_MSB 15 #define GTYE3_COM_QPLL0_FBDIV_G3_LSB 8 #define GTYE3_COM_QPLL0_FBDIV_G3_MASK BIT_MASK(GTYE3_COM_QPLL0_FBDIV_G3_MSB, GTYE3_COM_QPLL0_FBDIV_G3_LSB) #define GTYE3_COM_RXRECCLKOUT0_SEL_ADDR 0x001F #define GTYE3_COM_RXRECCLKOUT0_SEL_MSB 1 #define GTYE3_COM_RXRECCLKOUT0_SEL_LSB 0 #define GTYE3_COM_RXRECCLKOUT0_SEL_MASK BIT_MASK(GTYE3_COM_RXRECCLKOUT0_SEL_MSB, GTYE3_COM_RXRECCLKOUT0_SEL_LSB) #define GTYE3_COM_QPLL0_SDM_CFG0_ADDR 0x0020 #define GTYE3_COM_QPLL0_SDM_CFG0_MSB 15 #define GTYE3_COM_QPLL0_SDM_CFG0_LSB 0 #define GTYE3_COM_QPLL0_SDM_CFG0_MASK BIT_MASK(GTYE3_COM_QPLL0_SDM_CFG0_MSB, GTYE3_COM_QPLL0_SDM_CFG0_LSB) #define GTYE3_COM_QPLL0_SDM_CFG1_ADDR 0x0021 #define GTYE3_COM_QPLL0_SDM_CFG1_MSB 15 #define GTYE3_COM_QPLL0_SDM_CFG1_LSB 0 #define GTYE3_COM_QPLL0_SDM_CFG1_MASK BIT_MASK(GTYE3_COM_QPLL0_SDM_CFG1_MSB, GTYE3_COM_QPLL0_SDM_CFG1_LSB) #define GTYE3_COM_SDM0INITSEED0_0_ADDR 0x0022 #define GTYE3_COM_SDM0INITSEED0_0_MSB 15 #define GTYE3_COM_SDM0INITSEED0_0_LSB 0 #define GTYE3_COM_SDM0INITSEED0_0_MASK BIT_MASK(GTYE3_COM_SDM0INITSEED0_0_MSB, GTYE3_COM_SDM0INITSEED0_0_LSB) #define GTYE3_COM_SDM0INITSEED0_1_ADDR 0x0023 #define GTYE3_COM_SDM0INITSEED0_1_MSB 8 #define GTYE3_COM_SDM0INITSEED0_1_LSB 0 #define GTYE3_COM_SDM0INITSEED0_1_MASK BIT_MASK(GTYE3_COM_SDM0INITSEED0_1_MSB, GTYE3_COM_SDM0INITSEED0_1_LSB) #define GTYE3_COM_QPLL0_SDM_CFG2_ADDR 0x0024 #define GTYE3_COM_QPLL0_SDM_CFG2_MSB 15 #define GTYE3_COM_QPLL0_SDM_CFG2_LSB 0 #define GTYE3_COM_QPLL0_SDM_CFG2_MASK BIT_MASK(GTYE3_COM_QPLL0_SDM_CFG2_MSB, GTYE3_COM_QPLL0_SDM_CFG2_LSB) #define GTYE3_COM_QPLL0_CP_G3_ADDR 0x0025 #define GTYE3_COM_QPLL0_CP_G3_MSB 9 #define GTYE3_COM_QPLL0_CP_G3_LSB 0 #define GTYE3_COM_QPLL0_CP_G3_MASK BIT_MASK(GTYE3_COM_QPLL0_CP_G3_MSB, GTYE3_COM_QPLL0_CP_G3_LSB) #define GTYE3_COM_QPLL0_CFG4_ADDR 0x0030 #define GTYE3_COM_QPLL0_CFG4_MSB 15 #define GTYE3_COM_QPLL0_CFG4_LSB 0 #define GTYE3_COM_QPLL0_CFG4_MASK BIT_MASK(GTYE3_COM_QPLL0_CFG4_MSB, GTYE3_COM_QPLL0_CFG4_LSB) #define GTYE3_COM_BIAS_CFG0_ADDR 0x0081 #define GTYE3_COM_BIAS_CFG0_MSB 15 #define GTYE3_COM_BIAS_CFG0_LSB 0 #define GTYE3_COM_BIAS_CFG0_MASK BIT_MASK(GTYE3_COM_BIAS_CFG0_MSB, GTYE3_COM_BIAS_CFG0_LSB) #define GTYE3_COM_BIAS_CFG1_ADDR 0x0082 #define GTYE3_COM_BIAS_CFG1_MSB 15 #define GTYE3_COM_BIAS_CFG1_LSB 0 #define GTYE3_COM_BIAS_CFG1_MASK BIT_MASK(GTYE3_COM_BIAS_CFG1_MSB, GTYE3_COM_BIAS_CFG1_LSB) #define GTYE3_COM_BIAS_CFG2_ADDR 0x0083 #define GTYE3_COM_BIAS_CFG2_MSB 15 #define GTYE3_COM_BIAS_CFG2_LSB 0 #define GTYE3_COM_BIAS_CFG2_MASK BIT_MASK(GTYE3_COM_BIAS_CFG2_MSB, GTYE3_COM_BIAS_CFG2_LSB) #define GTYE3_COM_BIAS_CFG3_ADDR 0x0084 #define GTYE3_COM_BIAS_CFG3_MSB 15 #define GTYE3_COM_BIAS_CFG3_LSB 0 #define GTYE3_COM_BIAS_CFG3_MASK BIT_MASK(GTYE3_COM_BIAS_CFG3_MSB, GTYE3_COM_BIAS_CFG3_LSB) #define GTYE3_COM_BIAS_CFG4_ADDR 0x0086 #define GTYE3_COM_BIAS_CFG4_MSB 15 #define GTYE3_COM_BIAS_CFG4_LSB 0 #define GTYE3_COM_BIAS_CFG4_MASK BIT_MASK(GTYE3_COM_BIAS_CFG4_MSB, GTYE3_COM_BIAS_CFG4_LSB) #define GTYE3_COM_QPLL1_CFG0_ADDR 0x0088 #define GTYE3_COM_QPLL1_CFG0_MSB 15 #define GTYE3_COM_QPLL1_CFG0_LSB 0 #define GTYE3_COM_QPLL1_CFG0_MASK BIT_MASK(GTYE3_COM_QPLL1_CFG0_MSB, GTYE3_COM_QPLL1_CFG0_LSB) #define GTYE3_COM_COMMON_CFG1_ADDR 0x0089 #define GTYE3_COM_COMMON_CFG1_MSB 15 #define GTYE3_COM_COMMON_CFG1_LSB 0 #define GTYE3_COM_COMMON_CFG1_MASK BIT_MASK(GTYE3_COM_COMMON_CFG1_MSB, GTYE3_COM_COMMON_CFG1_LSB) #define GTYE3_COM_POR_CFG_ADDR 0x008B #define GTYE3_COM_POR_CFG_MSB 15 #define GTYE3_COM_POR_CFG_LSB 0 #define GTYE3_COM_POR_CFG_MASK BIT_MASK(GTYE3_COM_POR_CFG_MSB, GTYE3_COM_POR_CFG_LSB) #define GTYE3_COM_PPF1_CFG_ADDR 0x008D #define GTYE3_COM_PPF1_CFG_MSB 15 #define GTYE3_COM_PPF1_CFG_LSB 0 #define GTYE3_COM_PPF1_CFG_MASK BIT_MASK(GTYE3_COM_PPF1_CFG_MSB, GTYE3_COM_PPF1_CFG_LSB) #define GTYE3_COM_QPLL1CLKOUT_RATE_ADDR 0x008E #define GTYE3_COM_QPLL1CLKOUT_RATE_MSB 0 #define GTYE3_COM_QPLL1CLKOUT_RATE_LSB 0 #define GTYE3_COM_QPLL1CLKOUT_RATE_MASK BIT_MASK(GTYE3_COM_QPLL1CLKOUT_RATE_MSB, GTYE3_COM_QPLL1CLKOUT_RATE_LSB) #define GTYE3_COM_QPLL1CLKOUT_RATE_HALF 0 #define GTYE3_COM_QPLL1CLKOUT_RATE_FULL 1 #define GTYE3_COM_QPLL1_CFG1_ADDR 0x0090 #define GTYE3_COM_QPLL1_CFG1_MSB 15 #define GTYE3_COM_QPLL1_CFG1_LSB 0 #define GTYE3_COM_QPLL1_CFG1_MASK BIT_MASK(GTYE3_COM_QPLL1_CFG1_MSB, GTYE3_COM_QPLL1_CFG1_LSB) #define GTYE3_COM_QPLL1_CFG2_ADDR 0x0091 #define GTYE3_COM_QPLL1_CFG2_MSB 15 #define GTYE3_COM_QPLL1_CFG2_LSB 0 #define GTYE3_COM_QPLL1_CFG2_MASK BIT_MASK(GTYE3_COM_QPLL1_CFG2_MSB, GTYE3_COM_QPLL1_CFG2_LSB) #define GTYE3_COM_QPLL1_LOCK_CFG_ADDR 0x0092 #define GTYE3_COM_QPLL1_LOCK_CFG_MSB 15 #define GTYE3_COM_QPLL1_LOCK_CFG_LSB 0 #define GTYE3_COM_QPLL1_LOCK_CFG_MASK BIT_MASK(GTYE3_COM_QPLL1_LOCK_CFG_MSB, GTYE3_COM_QPLL1_LOCK_CFG_LSB) #define GTYE3_COM_QPLL1_INIT_CFG0_ADDR 0x0093 #define GTYE3_COM_QPLL1_INIT_CFG0_MSB 15 #define GTYE3_COM_QPLL1_INIT_CFG0_LSB 0 #define GTYE3_COM_QPLL1_INIT_CFG0_MASK BIT_MASK(GTYE3_COM_QPLL1_INIT_CFG0_MSB, GTYE3_COM_QPLL1_INIT_CFG0_LSB) #define GTYE3_COM_QPLL1_INIT_CFG1_ADDR 0x0094 #define GTYE3_COM_QPLL1_INIT_CFG1_MSB 15 #define GTYE3_COM_QPLL1_INIT_CFG1_LSB 8 #define GTYE3_COM_QPLL1_INIT_CFG1_MASK BIT_MASK(GTYE3_COM_QPLL1_INIT_CFG1_MSB, GTYE3_COM_QPLL1_INIT_CFG1_LSB) #define GTYE3_COM_QPLL1_FBDIV_ADDR 0x0094 #define GTYE3_COM_QPLL1_FBDIV_MSB 7 #define GTYE3_COM_QPLL1_FBDIV_LSB 0 #define GTYE3_COM_QPLL1_FBDIV_MASK BIT_MASK(GTYE3_COM_QPLL1_FBDIV_MSB, GTYE3_COM_QPLL1_FBDIV_LSB) #define GTYE3_COM_QPLL1_CFG3_ADDR 0x0095 #define GTYE3_COM_QPLL1_CFG3_MSB 15 #define GTYE3_COM_QPLL1_CFG3_LSB 0 #define GTYE3_COM_QPLL1_CFG3_MASK BIT_MASK(GTYE3_COM_QPLL1_CFG3_MSB, GTYE3_COM_QPLL1_CFG3_LSB) #define GTYE3_COM_QPLL1_CP_ADDR 0x0096 #define GTYE3_COM_QPLL1_CP_MSB 9 #define GTYE3_COM_QPLL1_CP_LSB 0 #define GTYE3_COM_QPLL1_CP_MASK BIT_MASK(GTYE3_COM_QPLL1_CP_MSB, GTYE3_COM_QPLL1_CP_LSB) #define GTYE3_COM_QPLL1_REFCLK_DIV_ADDR 0x0098 #define GTYE3_COM_QPLL1_REFCLK_DIV_MSB 11 #define GTYE3_COM_QPLL1_REFCLK_DIV_LSB 7 #define GTYE3_COM_QPLL1_REFCLK_DIV_MASK BIT_MASK(GTYE3_COM_QPLL1_REFCLK_DIV_MSB, GTYE3_COM_QPLL1_REFCLK_DIV_LSB) #define GTYE3_COM_QPLL1_REFCLK_DIV_1 16 #define GTYE3_COM_QPLL1_REFCLK_DIV_2 0 #define GTYE3_COM_QPLL1_REFCLK_DIV_3 1 #define GTYE3_COM_QPLL1_REFCLK_DIV_4 2 #define GTYE3_COM_QPLL1_REFCLK_DIV_5 3 #define GTYE3_COM_QPLL1_REFCLK_DIV_6 5 #define GTYE3_COM_QPLL1_REFCLK_DIV_8 6 #define GTYE3_COM_QPLL1_REFCLK_DIV_10 7 #define GTYE3_COM_QPLL1_REFCLK_DIV_12 13 #define GTYE3_COM_QPLL1_REFCLK_DIV_16 14 #define GTYE3_COM_QPLL1_REFCLK_DIV_20 15 #define GTYE3_COM_QPLL1_IPS_REFCLK_SEL_ADDR 0x0098 #define GTYE3_COM_QPLL1_IPS_REFCLK_SEL_MSB 5 #define GTYE3_COM_QPLL1_IPS_REFCLK_SEL_LSB 3 #define GTYE3_COM_QPLL1_IPS_REFCLK_SEL_MASK BIT_MASK(GTYE3_COM_QPLL1_IPS_REFCLK_SEL_MSB, GTYE3_COM_QPLL1_IPS_REFCLK_SEL_LSB) #define GTYE3_COM_SARC_EN_ADDR 0x0098 #define GTYE3_COM_SARC_EN_MSB 12 #define GTYE3_COM_SARC_EN_LSB 12 #define GTYE3_COM_SARC_EN_MASK BIT_MASK(GTYE3_COM_SARC_EN_MSB, GTYE3_COM_SARC_EN_LSB) #define GTYE3_COM_QPLL1_IPS_EN_ADDR 0x0098 #define GTYE3_COM_QPLL1_IPS_EN_MSB 6 #define GTYE3_COM_QPLL1_IPS_EN_LSB 6 #define GTYE3_COM_QPLL1_IPS_EN_MASK BIT_MASK(GTYE3_COM_QPLL1_IPS_EN_MSB, GTYE3_COM_QPLL1_IPS_EN_LSB) #define GTYE3_COM_SARC_SEL_ADDR 0x0098 #define GTYE3_COM_SARC_SEL_MSB 13 #define GTYE3_COM_SARC_SEL_LSB 13 #define GTYE3_COM_SARC_SEL_MASK BIT_MASK(GTYE3_COM_SARC_SEL_MSB, GTYE3_COM_SARC_SEL_LSB) #define GTYE3_COM_QPLL1_LPF_ADDR 0x0099 #define GTYE3_COM_QPLL1_LPF_MSB 15 #define GTYE3_COM_QPLL1_LPF_LSB 0 #define GTYE3_COM_QPLL1_LPF_MASK BIT_MASK(GTYE3_COM_QPLL1_LPF_MSB, GTYE3_COM_QPLL1_LPF_LSB) #define GTYE3_COM_QPLL1_CFG1_G3_ADDR 0x009A #define GTYE3_COM_QPLL1_CFG1_G3_MSB 15 #define GTYE3_COM_QPLL1_CFG1_G3_LSB 0 #define GTYE3_COM_QPLL1_CFG1_G3_MASK BIT_MASK(GTYE3_COM_QPLL1_CFG1_G3_MSB, GTYE3_COM_QPLL1_CFG1_G3_LSB) #define GTYE3_COM_QPLL1_CFG2_G3_ADDR 0x009B #define GTYE3_COM_QPLL1_CFG2_G3_MSB 15 #define GTYE3_COM_QPLL1_CFG2_G3_LSB 0 #define GTYE3_COM_QPLL1_CFG2_G3_MASK BIT_MASK(GTYE3_COM_QPLL1_CFG2_G3_MSB, GTYE3_COM_QPLL1_CFG2_G3_LSB) #define GTYE3_COM_QPLL1_LPF_G3_ADDR 0x009C #define GTYE3_COM_QPLL1_LPF_G3_MSB 9 #define GTYE3_COM_QPLL1_LPF_G3_LSB 0 #define GTYE3_COM_QPLL1_LPF_G3_MASK BIT_MASK(GTYE3_COM_QPLL1_LPF_G3_MSB, GTYE3_COM_QPLL1_LPF_G3_LSB) #define GTYE3_COM_QPLL1_LOCK_CFG_G3_ADDR 0x009D #define GTYE3_COM_QPLL1_LOCK_CFG_G3_MSB 15 #define GTYE3_COM_QPLL1_LOCK_CFG_G3_LSB 0 #define GTYE3_COM_QPLL1_LOCK_CFG_G3_MASK BIT_MASK(GTYE3_COM_QPLL1_LOCK_CFG_G3_MSB, GTYE3_COM_QPLL1_LOCK_CFG_G3_LSB) #define GTYE3_COM_RSVD_ATTR2_ADDR 0x009E #define GTYE3_COM_RSVD_ATTR2_MSB 15 #define GTYE3_COM_RSVD_ATTR2_LSB 0 #define GTYE3_COM_RSVD_ATTR2_MASK BIT_MASK(GTYE3_COM_RSVD_ATTR2_MSB, GTYE3_COM_RSVD_ATTR2_LSB) #define GTYE3_COM_QPLL1_FBDIV_G3_ADDR 0x009F #define GTYE3_COM_QPLL1_FBDIV_G3_MSB 15 #define GTYE3_COM_QPLL1_FBDIV_G3_LSB 8 #define GTYE3_COM_QPLL1_FBDIV_G3_MASK BIT_MASK(GTYE3_COM_QPLL1_FBDIV_G3_MSB, GTYE3_COM_QPLL1_FBDIV_G3_LSB) #define GTYE3_COM_RXRECCLKOUT1_SEL_ADDR 0x009F #define GTYE3_COM_RXRECCLKOUT1_SEL_MSB 1 #define GTYE3_COM_RXRECCLKOUT1_SEL_LSB 0 #define GTYE3_COM_RXRECCLKOUT1_SEL_MASK BIT_MASK(GTYE3_COM_RXRECCLKOUT1_SEL_MSB, GTYE3_COM_RXRECCLKOUT1_SEL_LSB) #define GTYE3_COM_QPLL1_SDM_CFG0_ADDR 0x00A0 #define GTYE3_COM_QPLL1_SDM_CFG0_MSB 15 #define GTYE3_COM_QPLL1_SDM_CFG0_LSB 0 #define GTYE3_COM_QPLL1_SDM_CFG0_MASK BIT_MASK(GTYE3_COM_QPLL1_SDM_CFG0_MSB, GTYE3_COM_QPLL1_SDM_CFG0_LSB) #define GTYE3_COM_QPLL1_SDM_CFG1_ADDR 0x00A1 #define GTYE3_COM_QPLL1_SDM_CFG1_MSB 15 #define GTYE3_COM_QPLL1_SDM_CFG1_LSB 0 #define GTYE3_COM_QPLL1_SDM_CFG1_MASK BIT_MASK(GTYE3_COM_QPLL1_SDM_CFG1_MSB, GTYE3_COM_QPLL1_SDM_CFG1_LSB) #define GTYE3_COM_SDM1INITSEED0_0_ADDR 0x00A2 #define GTYE3_COM_SDM1INITSEED0_0_MSB 15 #define GTYE3_COM_SDM1INITSEED0_0_LSB 0 #define GTYE3_COM_SDM1INITSEED0_0_MASK BIT_MASK(GTYE3_COM_SDM1INITSEED0_0_MSB, GTYE3_COM_SDM1INITSEED0_0_LSB) #define GTYE3_COM_SDM1INITSEED0_1_ADDR 0x00A3 #define GTYE3_COM_SDM1INITSEED0_1_MSB 8 #define GTYE3_COM_SDM1INITSEED0_1_LSB 0 #define GTYE3_COM_SDM1INITSEED0_1_MASK BIT_MASK(GTYE3_COM_SDM1INITSEED0_1_MSB, GTYE3_COM_SDM1INITSEED0_1_LSB) #define GTYE3_COM_QPLL1_SDM_CFG2_ADDR 0x00A4 #define GTYE3_COM_QPLL1_SDM_CFG2_MSB 15 #define GTYE3_COM_QPLL1_SDM_CFG2_LSB 0 #define GTYE3_COM_QPLL1_SDM_CFG2_MASK BIT_MASK(GTYE3_COM_QPLL1_SDM_CFG2_MSB, GTYE3_COM_QPLL1_SDM_CFG2_LSB) #define GTYE3_COM_QPLL1_CP_G3_ADDR 0x00A5 #define GTYE3_COM_QPLL1_CP_G3_MSB 9 #define GTYE3_COM_QPLL1_CP_G3_LSB 0 #define GTYE3_COM_QPLL1_CP_G3_MASK BIT_MASK(GTYE3_COM_QPLL1_CP_G3_MSB, GTYE3_COM_QPLL1_CP_G3_LSB) #define GTYE3_COM_RSVD_ATTR3_ADDR 0x00AD #define GTYE3_COM_RSVD_ATTR3_MSB 15 #define GTYE3_COM_RSVD_ATTR3_LSB 0 #define GTYE3_COM_RSVD_ATTR3_MASK BIT_MASK(GTYE3_COM_RSVD_ATTR3_MSB, GTYE3_COM_RSVD_ATTR3_LSB) #define GTYE3_COM_QPLL1_CFG4_ADDR 0x00B0 #define GTYE3_COM_QPLL1_CFG4_MSB 15 #define GTYE3_COM_QPLL1_CFG4_LSB 0 #define GTYE3_COM_QPLL1_CFG4_MASK BIT_MASK(GTYE3_COM_QPLL1_CFG4_MSB, GTYE3_COM_QPLL1_CFG4_LSB) // channel registers #define GTYE3_CH_CDR_SWAP_MODE_EN_ADDR 0x0002 #define GTYE3_CH_CDR_SWAP_MODE_EN_MSB 0 #define GTYE3_CH_CDR_SWAP_MODE_EN_LSB 0 #define GTYE3_CH_CDR_SWAP_MODE_EN_MASK BIT_MASK(GTYE3_CH_CDR_SWAP_MODE_EN_MSB, GTYE3_CH_CDR_SWAP_MODE_EN_LSB) #define GTYE3_CH_RXBUFRESET_TIME_ADDR 0x0003 #define GTYE3_CH_RXBUFRESET_TIME_MSB 15 #define GTYE3_CH_RXBUFRESET_TIME_LSB 11 #define GTYE3_CH_RXBUFRESET_TIME_MASK BIT_MASK(GTYE3_CH_RXBUFRESET_TIME_MSB, GTYE3_CH_RXBUFRESET_TIME_LSB) #define GTYE3_CH_EYE_SCAN_SWAP_EN_ADDR 0x0003 #define GTYE3_CH_EYE_SCAN_SWAP_EN_MSB 9 #define GTYE3_CH_EYE_SCAN_SWAP_EN_LSB 9 #define GTYE3_CH_EYE_SCAN_SWAP_EN_MASK BIT_MASK(GTYE3_CH_EYE_SCAN_SWAP_EN_MSB, GTYE3_CH_EYE_SCAN_SWAP_EN_LSB) #define GTYE3_CH_RX_DATA_WIDTH_ADDR 0x0003 #define GTYE3_CH_RX_DATA_WIDTH_MSB 8 #define GTYE3_CH_RX_DATA_WIDTH_LSB 5 #define GTYE3_CH_RX_DATA_WIDTH_MASK BIT_MASK(GTYE3_CH_RX_DATA_WIDTH_MSB, GTYE3_CH_RX_DATA_WIDTH_LSB) #define GTYE3_CH_RX_DATA_WIDTH_16 2 #define GTYE3_CH_RX_DATA_WIDTH_20 3 #define GTYE3_CH_RX_DATA_WIDTH_32 4 #define GTYE3_CH_RX_DATA_WIDTH_40 5 #define GTYE3_CH_RX_DATA_WIDTH_64 6 #define GTYE3_CH_RX_DATA_WIDTH_80 7 #define GTYE3_CH_RX_DATA_WIDTH_128 8 #define GTYE3_CH_RX_DATA_WIDTH_160 9 #define GTYE3_CH_RXCDRFREQRESET_TIME_ADDR 0x0003 #define GTYE3_CH_RXCDRFREQRESET_TIME_MSB 4 #define GTYE3_CH_RXCDRFREQRESET_TIME_LSB 0 #define GTYE3_CH_RXCDRFREQRESET_TIME_MASK BIT_MASK(GTYE3_CH_RXCDRFREQRESET_TIME_MSB, GTYE3_CH_RXCDRFREQRESET_TIME_LSB) #define GTYE3_CH_RXCDRPHRESET_TIME_ADDR 0x0004 #define GTYE3_CH_RXCDRPHRESET_TIME_MSB 15 #define GTYE3_CH_RXCDRPHRESET_TIME_LSB 11 #define GTYE3_CH_RXCDRPHRESET_TIME_MASK BIT_MASK(GTYE3_CH_RXCDRPHRESET_TIME_MSB, GTYE3_CH_RXCDRPHRESET_TIME_LSB) #define GTYE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_ADDR 0x0004 #define GTYE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_MSB 10 #define GTYE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_LSB 8 #define GTYE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_MASK BIT_MASK(GTYE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_MSB, GTYE3_CH_PCI3_RX_ELECIDLE_H2L_DISABLE_LSB) #define GTYE3_CH_RXDFELPMRESET_TIME_ADDR 0x0004 #define GTYE3_CH_RXDFELPMRESET_TIME_MSB 7 #define GTYE3_CH_RXDFELPMRESET_TIME_LSB 1 #define GTYE3_CH_RXDFELPMRESET_TIME_MASK BIT_MASK(GTYE3_CH_RXDFELPMRESET_TIME_MSB, GTYE3_CH_RXDFELPMRESET_TIME_LSB) #define GTYE3_CH_RX_FABINT_USRCLK_FLOP_ADDR 0x0004 #define GTYE3_CH_RX_FABINT_USRCLK_FLOP_MSB 0 #define GTYE3_CH_RX_FABINT_USRCLK_FLOP_LSB 0 #define GTYE3_CH_RX_FABINT_USRCLK_FLOP_MASK BIT_MASK(GTYE3_CH_RX_FABINT_USRCLK_FLOP_MSB, GTYE3_CH_RX_FABINT_USRCLK_FLOP_LSB) #define GTYE3_CH_RXPMARESET_TIME_ADDR 0x0005 #define GTYE3_CH_RXPMARESET_TIME_MSB 15 #define GTYE3_CH_RXPMARESET_TIME_LSB 11 #define GTYE3_CH_RXPMARESET_TIME_MASK BIT_MASK(GTYE3_CH_RXPMARESET_TIME_MSB, GTYE3_CH_RXPMARESET_TIME_LSB) #define GTYE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_ADDR 0x0005 #define GTYE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_MSB 10 #define GTYE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_LSB 10 #define GTYE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_MASK BIT_MASK(GTYE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_MSB, GTYE3_CH_PCI3_RX_ELECIDLE_LP4_DISABLE_LSB) #define GTYE3_CH_PCI3_RX_FIFO_DISABLE_ADDR 0x0005 #define GTYE3_CH_PCI3_RX_FIFO_DISABLE_MSB 8 #define GTYE3_CH_PCI3_RX_FIFO_DISABLE_LSB 8 #define GTYE3_CH_PCI3_RX_FIFO_DISABLE_MASK BIT_MASK(GTYE3_CH_PCI3_RX_FIFO_DISABLE_MSB, GTYE3_CH_PCI3_RX_FIFO_DISABLE_LSB) #define GTYE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_ADDR 0x0005 #define GTYE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_MSB 9 #define GTYE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_LSB 9 #define GTYE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_MASK BIT_MASK(GTYE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_MSB, GTYE3_CH_PCI3_RX_ELECIDLE_EI2_ENABLE_LSB) #define GTYE3_CH_RXPCSRESET_TIME_ADDR 0x0005 #define GTYE3_CH_RXPCSRESET_TIME_MSB 7 #define GTYE3_CH_RXPCSRESET_TIME_LSB 3 #define GTYE3_CH_RXPCSRESET_TIME_MASK BIT_MASK(GTYE3_CH_RXPCSRESET_TIME_MSB, GTYE3_CH_RXPCSRESET_TIME_LSB) #define GTYE3_CH_RXELECIDLE_CFG_ADDR 0x0005 #define GTYE3_CH_RXELECIDLE_CFG_MSB 2 #define GTYE3_CH_RXELECIDLE_CFG_LSB 0 #define GTYE3_CH_RXELECIDLE_CFG_MASK BIT_MASK(GTYE3_CH_RXELECIDLE_CFG_MSB, GTYE3_CH_RXELECIDLE_CFG_LSB) #define GTYE3_CH_RXELECIDLE_CFG_SIGCFG_1 0 #define GTYE3_CH_RXELECIDLE_CFG_SIGCFG_2 1 #define GTYE3_CH_RXELECIDLE_CFG_SIGCFG_3 2 #define GTYE3_CH_RXELECIDLE_CFG_SIGCFG_4 3 #define GTYE3_CH_RXELECIDLE_CFG_SIGCFG_6 4 #define GTYE3_CH_RXELECIDLE_CFG_SIGCFG_8 5 #define GTYE3_CH_RXELECIDLE_CFG_SIGCFG_12 6 #define GTYE3_CH_RXELECIDLE_CFG_SIGCFG_16 7 #define GTYE3_CH_RXDFE_HB_CFG1_ADDR 0x0006 #define GTYE3_CH_RXDFE_HB_CFG1_MSB 15 #define GTYE3_CH_RXDFE_HB_CFG1_LSB 0 #define GTYE3_CH_RXDFE_HB_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_HB_CFG1_MSB, GTYE3_CH_RXDFE_HB_CFG1_LSB) #define GTYE3_CH_TXPMARESET_TIME_ADDR 0x0009 #define GTYE3_CH_TXPMARESET_TIME_MSB 15 #define GTYE3_CH_TXPMARESET_TIME_LSB 11 #define GTYE3_CH_TXPMARESET_TIME_MASK BIT_MASK(GTYE3_CH_TXPMARESET_TIME_MSB, GTYE3_CH_TXPMARESET_TIME_LSB) #define GTYE3_CH_TXPCSRESET_TIME_ADDR 0x0009 #define GTYE3_CH_TXPCSRESET_TIME_MSB 7 #define GTYE3_CH_TXPCSRESET_TIME_LSB 3 #define GTYE3_CH_TXPCSRESET_TIME_MASK BIT_MASK(GTYE3_CH_TXPCSRESET_TIME_MSB, GTYE3_CH_TXPCSRESET_TIME_LSB) #define GTYE3_CH_RX_PMA_POWER_SAVE_ADDR 0x0009 #define GTYE3_CH_RX_PMA_POWER_SAVE_MSB 10 #define GTYE3_CH_RX_PMA_POWER_SAVE_LSB 10 #define GTYE3_CH_RX_PMA_POWER_SAVE_MASK BIT_MASK(GTYE3_CH_RX_PMA_POWER_SAVE_MSB, GTYE3_CH_RX_PMA_POWER_SAVE_LSB) #define GTYE3_CH_TX_PMA_POWER_SAVE_ADDR 0x0009 #define GTYE3_CH_TX_PMA_POWER_SAVE_MSB 9 #define GTYE3_CH_TX_PMA_POWER_SAVE_LSB 9 #define GTYE3_CH_TX_PMA_POWER_SAVE_MASK BIT_MASK(GTYE3_CH_TX_PMA_POWER_SAVE_MSB, GTYE3_CH_TX_PMA_POWER_SAVE_LSB) #define GTYE3_CH_TX_FABINT_USRCLK_FLOP_ADDR 0x000B #define GTYE3_CH_TX_FABINT_USRCLK_FLOP_MSB 4 #define GTYE3_CH_TX_FABINT_USRCLK_FLOP_LSB 4 #define GTYE3_CH_TX_FABINT_USRCLK_FLOP_MASK BIT_MASK(GTYE3_CH_TX_FABINT_USRCLK_FLOP_MSB, GTYE3_CH_TX_FABINT_USRCLK_FLOP_LSB) #define GTYE3_CH_RXPMACLK_SEL_ADDR 0x000B #define GTYE3_CH_RXPMACLK_SEL_MSB 9 #define GTYE3_CH_RXPMACLK_SEL_LSB 8 #define GTYE3_CH_RXPMACLK_SEL_MASK BIT_MASK(GTYE3_CH_RXPMACLK_SEL_MSB, GTYE3_CH_RXPMACLK_SEL_LSB) #define GTYE3_CH_RXPMACLK_SEL_DATA 0 #define GTYE3_CH_RXPMACLK_SEL_EYESCAN 1 #define GTYE3_CH_RXPMACLK_SEL_CROSSING 2 #define GTYE3_CH_TX_PROGCLK_SEL_ADDR 0x000C #define GTYE3_CH_TX_PROGCLK_SEL_MSB 11 #define GTYE3_CH_TX_PROGCLK_SEL_LSB 10 #define GTYE3_CH_TX_PROGCLK_SEL_MASK BIT_MASK(GTYE3_CH_TX_PROGCLK_SEL_MSB, GTYE3_CH_TX_PROGCLK_SEL_LSB) #define GTYE3_CH_TX_PROGCLK_SEL_POSTPI 0 #define GTYE3_CH_TX_PROGCLK_SEL_PREPI 1 #define GTYE3_CH_TX_PROGCLK_SEL_CPLL 2 #define GTYE3_CH_RXISCANRESET_TIME_ADDR 0x000C #define GTYE3_CH_RXISCANRESET_TIME_MSB 9 #define GTYE3_CH_RXISCANRESET_TIME_LSB 5 #define GTYE3_CH_RXISCANRESET_TIME_MASK BIT_MASK(GTYE3_CH_RXISCANRESET_TIME_MSB, GTYE3_CH_RXISCANRESET_TIME_LSB) #define GTYE3_CH_RXCDR_CFG0_ADDR 0x000E #define GTYE3_CH_RXCDR_CFG0_MSB 15 #define GTYE3_CH_RXCDR_CFG0_LSB 0 #define GTYE3_CH_RXCDR_CFG0_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG0_MSB, GTYE3_CH_RXCDR_CFG0_LSB) #define GTYE3_CH_RXCDR_CFG1_ADDR 0x000F #define GTYE3_CH_RXCDR_CFG1_MSB 15 #define GTYE3_CH_RXCDR_CFG1_LSB 0 #define GTYE3_CH_RXCDR_CFG1_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG1_MSB, GTYE3_CH_RXCDR_CFG1_LSB) #define GTYE3_CH_RXCDR_CFG2_ADDR 0x0010 #define GTYE3_CH_RXCDR_CFG2_MSB 15 #define GTYE3_CH_RXCDR_CFG2_LSB 0 #define GTYE3_CH_RXCDR_CFG2_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG2_MSB, GTYE3_CH_RXCDR_CFG2_LSB) #define GTYE3_CH_RXCDR_CFG3_ADDR 0x0011 #define GTYE3_CH_RXCDR_CFG3_MSB 15 #define GTYE3_CH_RXCDR_CFG3_LSB 0 #define GTYE3_CH_RXCDR_CFG3_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG3_MSB, GTYE3_CH_RXCDR_CFG3_LSB) #define GTYE3_CH_RXCDR_CFG4_ADDR 0x0012 #define GTYE3_CH_RXCDR_CFG4_MSB 15 #define GTYE3_CH_RXCDR_CFG4_LSB 0 #define GTYE3_CH_RXCDR_CFG4_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG4_MSB, GTYE3_CH_RXCDR_CFG4_LSB) #define GTYE3_CH_RXCDR_LOCK_CFG0_ADDR 0x0013 #define GTYE3_CH_RXCDR_LOCK_CFG0_MSB 15 #define GTYE3_CH_RXCDR_LOCK_CFG0_LSB 0 #define GTYE3_CH_RXCDR_LOCK_CFG0_MASK BIT_MASK(GTYE3_CH_RXCDR_LOCK_CFG0_MSB, GTYE3_CH_RXCDR_LOCK_CFG0_LSB) #define GTYE3_CH_CHAN_BOND_MAX_SKEW_ADDR 0x0014 #define GTYE3_CH_CHAN_BOND_MAX_SKEW_MSB 15 #define GTYE3_CH_CHAN_BOND_MAX_SKEW_LSB 12 #define GTYE3_CH_CHAN_BOND_MAX_SKEW_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_MAX_SKEW_MSB, GTYE3_CH_CHAN_BOND_MAX_SKEW_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_LEN_ADDR 0x0014 #define GTYE3_CH_CHAN_BOND_SEQ_LEN_MSB 11 #define GTYE3_CH_CHAN_BOND_SEQ_LEN_LSB 10 #define GTYE3_CH_CHAN_BOND_SEQ_LEN_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_LEN_MSB, GTYE3_CH_CHAN_BOND_SEQ_LEN_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_LEN_1 0 #define GTYE3_CH_CHAN_BOND_SEQ_LEN_2 1 #define GTYE3_CH_CHAN_BOND_SEQ_LEN_3 2 #define GTYE3_CH_CHAN_BOND_SEQ_LEN_4 3 #define GTYE3_CH_CHAN_BOND_SEQ_1_1_ADDR 0x0014 #define GTYE3_CH_CHAN_BOND_SEQ_1_1_MSB 9 #define GTYE3_CH_CHAN_BOND_SEQ_1_1_LSB 0 #define GTYE3_CH_CHAN_BOND_SEQ_1_1_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_1_1_MSB, GTYE3_CH_CHAN_BOND_SEQ_1_1_LSB) #define GTYE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_ADDR 0x0015 #define GTYE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_MSB 15 #define GTYE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_LSB 10 #define GTYE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_MASK BIT_MASK(GTYE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_MSB, GTYE3_CH_PCI3_RX_ELECIDLE_HI_COUNT_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_1_3_ADDR 0x0015 #define GTYE3_CH_CHAN_BOND_SEQ_1_3_MSB 9 #define GTYE3_CH_CHAN_BOND_SEQ_1_3_LSB 0 #define GTYE3_CH_CHAN_BOND_SEQ_1_3_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_1_3_MSB, GTYE3_CH_CHAN_BOND_SEQ_1_3_LSB) #define GTYE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_ADDR 0x0016 #define GTYE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_MSB 15 #define GTYE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_LSB 10 #define GTYE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_MASK BIT_MASK(GTYE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_MSB, GTYE3_CH_PCI3_RX_ELECIDLE_H2L_COUNT_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_1_4_ADDR 0x0016 #define GTYE3_CH_CHAN_BOND_SEQ_1_4_MSB 9 #define GTYE3_CH_CHAN_BOND_SEQ_1_4_LSB 0 #define GTYE3_CH_CHAN_BOND_SEQ_1_4_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_1_4_MSB, GTYE3_CH_CHAN_BOND_SEQ_1_4_LSB) #define GTYE3_CH_RX_BUFFER_CFG_ADDR 0x0017 #define GTYE3_CH_RX_BUFFER_CFG_MSB 15 #define GTYE3_CH_RX_BUFFER_CFG_LSB 10 #define GTYE3_CH_RX_BUFFER_CFG_MASK BIT_MASK(GTYE3_CH_RX_BUFFER_CFG_MSB, GTYE3_CH_RX_BUFFER_CFG_LSB) #define GTYE3_CH_RX_DEFER_RESET_BUF_EN_ADDR 0x0017 #define GTYE3_CH_RX_DEFER_RESET_BUF_EN_MSB 9 #define GTYE3_CH_RX_DEFER_RESET_BUF_EN_LSB 9 #define GTYE3_CH_RX_DEFER_RESET_BUF_EN_MASK BIT_MASK(GTYE3_CH_RX_DEFER_RESET_BUF_EN_MSB, GTYE3_CH_RX_DEFER_RESET_BUF_EN_LSB) #define GTYE3_CH_OOBDIVCTL_ADDR 0x0017 #define GTYE3_CH_OOBDIVCTL_MSB 8 #define GTYE3_CH_OOBDIVCTL_LSB 7 #define GTYE3_CH_OOBDIVCTL_MASK BIT_MASK(GTYE3_CH_OOBDIVCTL_MSB, GTYE3_CH_OOBDIVCTL_LSB) #define GTYE3_CH_PCI3_AUTO_REALIGN_ADDR 0x0017 #define GTYE3_CH_PCI3_AUTO_REALIGN_MSB 6 #define GTYE3_CH_PCI3_AUTO_REALIGN_LSB 5 #define GTYE3_CH_PCI3_AUTO_REALIGN_MASK BIT_MASK(GTYE3_CH_PCI3_AUTO_REALIGN_MSB, GTYE3_CH_PCI3_AUTO_REALIGN_LSB) #define GTYE3_CH_PCI3_AUTO_REALIGN_FRST_SMPL 0 #define GTYE3_CH_PCI3_AUTO_REALIGN_OVR_8_BLK 1 #define GTYE3_CH_PCI3_AUTO_REALIGN_OVR_64_BLK 2 #define GTYE3_CH_PCI3_AUTO_REALIGN_OVR_1K_BLK 3 #define GTYE3_CH_PCI3_PIPE_RX_ELECIDLE_ADDR 0x0017 #define GTYE3_CH_PCI3_PIPE_RX_ELECIDLE_MSB 4 #define GTYE3_CH_PCI3_PIPE_RX_ELECIDLE_LSB 4 #define GTYE3_CH_PCI3_PIPE_RX_ELECIDLE_MASK BIT_MASK(GTYE3_CH_PCI3_PIPE_RX_ELECIDLE_MSB, GTYE3_CH_PCI3_PIPE_RX_ELECIDLE_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_1_ENABLE_ADDR 0x0018 #define GTYE3_CH_CHAN_BOND_SEQ_1_ENABLE_MSB 15 #define GTYE3_CH_CHAN_BOND_SEQ_1_ENABLE_LSB 12 #define GTYE3_CH_CHAN_BOND_SEQ_1_ENABLE_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_1_ENABLE_MSB, GTYE3_CH_CHAN_BOND_SEQ_1_ENABLE_LSB) #define GTYE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_ADDR 0x0018 #define GTYE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_MSB 11 #define GTYE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_LSB 10 #define GTYE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_MASK BIT_MASK(GTYE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_MSB, GTYE3_CH_PCI3_RX_ASYNC_EBUF_BYPASS_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_2_1_ADDR 0x0018 #define GTYE3_CH_CHAN_BOND_SEQ_2_1_MSB 9 #define GTYE3_CH_CHAN_BOND_SEQ_2_1_LSB 0 #define GTYE3_CH_CHAN_BOND_SEQ_2_1_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_2_1_MSB, GTYE3_CH_CHAN_BOND_SEQ_2_1_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_2_2_ADDR 0x0019 #define GTYE3_CH_CHAN_BOND_SEQ_2_2_MSB 9 #define GTYE3_CH_CHAN_BOND_SEQ_2_2_LSB 0 #define GTYE3_CH_CHAN_BOND_SEQ_2_2_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_2_2_MSB, GTYE3_CH_CHAN_BOND_SEQ_2_2_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_2_3_ADDR 0x001A #define GTYE3_CH_CHAN_BOND_SEQ_2_3_MSB 9 #define GTYE3_CH_CHAN_BOND_SEQ_2_3_LSB 0 #define GTYE3_CH_CHAN_BOND_SEQ_2_3_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_2_3_MSB, GTYE3_CH_CHAN_BOND_SEQ_2_3_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_2_4_ADDR 0x001B #define GTYE3_CH_CHAN_BOND_SEQ_2_4_MSB 9 #define GTYE3_CH_CHAN_BOND_SEQ_2_4_LSB 0 #define GTYE3_CH_CHAN_BOND_SEQ_2_4_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_2_4_MSB, GTYE3_CH_CHAN_BOND_SEQ_2_4_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_2_ENABLE_ADDR 0x001C #define GTYE3_CH_CHAN_BOND_SEQ_2_ENABLE_MSB 15 #define GTYE3_CH_CHAN_BOND_SEQ_2_ENABLE_LSB 12 #define GTYE3_CH_CHAN_BOND_SEQ_2_ENABLE_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_2_ENABLE_MSB, GTYE3_CH_CHAN_BOND_SEQ_2_ENABLE_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_2_USE_ADDR 0x001C #define GTYE3_CH_CHAN_BOND_SEQ_2_USE_MSB 11 #define GTYE3_CH_CHAN_BOND_SEQ_2_USE_LSB 11 #define GTYE3_CH_CHAN_BOND_SEQ_2_USE_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_2_USE_MSB, GTYE3_CH_CHAN_BOND_SEQ_2_USE_LSB) #define GTYE3_CH_CLK_COR_KEEP_IDLE_ADDR 0x001C #define GTYE3_CH_CLK_COR_KEEP_IDLE_MSB 6 #define GTYE3_CH_CLK_COR_KEEP_IDLE_LSB 6 #define GTYE3_CH_CLK_COR_KEEP_IDLE_MASK BIT_MASK(GTYE3_CH_CLK_COR_KEEP_IDLE_MSB, GTYE3_CH_CLK_COR_KEEP_IDLE_LSB) #define GTYE3_CH_CLK_COR_MIN_LAT_ADDR 0x001C #define GTYE3_CH_CLK_COR_MIN_LAT_MSB 5 #define GTYE3_CH_CLK_COR_MIN_LAT_LSB 0 #define GTYE3_CH_CLK_COR_MIN_LAT_MASK BIT_MASK(GTYE3_CH_CLK_COR_MIN_LAT_MSB, GTYE3_CH_CLK_COR_MIN_LAT_LSB) #define GTYE3_CH_CLK_COR_MAX_LAT_ADDR 0x001D #define GTYE3_CH_CLK_COR_MAX_LAT_MSB 15 #define GTYE3_CH_CLK_COR_MAX_LAT_LSB 10 #define GTYE3_CH_CLK_COR_MAX_LAT_MASK BIT_MASK(GTYE3_CH_CLK_COR_MAX_LAT_MSB, GTYE3_CH_CLK_COR_MAX_LAT_LSB) #define GTYE3_CH_CLK_COR_PRECEDENCE_ADDR 0x001D #define GTYE3_CH_CLK_COR_PRECEDENCE_MSB 9 #define GTYE3_CH_CLK_COR_PRECEDENCE_LSB 9 #define GTYE3_CH_CLK_COR_PRECEDENCE_MASK BIT_MASK(GTYE3_CH_CLK_COR_PRECEDENCE_MSB, GTYE3_CH_CLK_COR_PRECEDENCE_LSB) #define GTYE3_CH_CLK_COR_REPEAT_WAIT_ADDR 0x001D #define GTYE3_CH_CLK_COR_REPEAT_WAIT_MSB 8 #define GTYE3_CH_CLK_COR_REPEAT_WAIT_LSB 4 #define GTYE3_CH_CLK_COR_REPEAT_WAIT_MASK BIT_MASK(GTYE3_CH_CLK_COR_REPEAT_WAIT_MSB, GTYE3_CH_CLK_COR_REPEAT_WAIT_LSB) #define GTYE3_CH_CLK_COR_SEQ_LEN_ADDR 0x001D #define GTYE3_CH_CLK_COR_SEQ_LEN_MSB 3 #define GTYE3_CH_CLK_COR_SEQ_LEN_LSB 2 #define GTYE3_CH_CLK_COR_SEQ_LEN_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_LEN_MSB, GTYE3_CH_CLK_COR_SEQ_LEN_LSB) #define GTYE3_CH_CLK_COR_SEQ_LEN_1 0 #define GTYE3_CH_CLK_COR_SEQ_LEN_2 1 #define GTYE3_CH_CLK_COR_SEQ_LEN_3 2 #define GTYE3_CH_CLK_COR_SEQ_LEN_4 3 #define GTYE3_CH_CHAN_BOND_KEEP_ALIGN_ADDR 0x001D #define GTYE3_CH_CHAN_BOND_KEEP_ALIGN_MSB 0 #define GTYE3_CH_CHAN_BOND_KEEP_ALIGN_LSB 0 #define GTYE3_CH_CHAN_BOND_KEEP_ALIGN_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_KEEP_ALIGN_MSB, GTYE3_CH_CHAN_BOND_KEEP_ALIGN_LSB) #define GTYE3_CH_CLK_COR_SEQ_1_1_ADDR 0x001E #define GTYE3_CH_CLK_COR_SEQ_1_1_MSB 9 #define GTYE3_CH_CLK_COR_SEQ_1_1_LSB 0 #define GTYE3_CH_CLK_COR_SEQ_1_1_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_1_1_MSB, GTYE3_CH_CLK_COR_SEQ_1_1_LSB) #define GTYE3_CH_CLK_COR_SEQ_1_2_ADDR 0x001F #define GTYE3_CH_CLK_COR_SEQ_1_2_MSB 9 #define GTYE3_CH_CLK_COR_SEQ_1_2_LSB 0 #define GTYE3_CH_CLK_COR_SEQ_1_2_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_1_2_MSB, GTYE3_CH_CLK_COR_SEQ_1_2_LSB) #define GTYE3_CH_CLK_COR_SEQ_1_3_ADDR 0x0020 #define GTYE3_CH_CLK_COR_SEQ_1_3_MSB 9 #define GTYE3_CH_CLK_COR_SEQ_1_3_LSB 0 #define GTYE3_CH_CLK_COR_SEQ_1_3_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_1_3_MSB, GTYE3_CH_CLK_COR_SEQ_1_3_LSB) #define GTYE3_CH_CLK_COR_SEQ_1_4_ADDR 0x0021 #define GTYE3_CH_CLK_COR_SEQ_1_4_MSB 9 #define GTYE3_CH_CLK_COR_SEQ_1_4_LSB 0 #define GTYE3_CH_CLK_COR_SEQ_1_4_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_1_4_MSB, GTYE3_CH_CLK_COR_SEQ_1_4_LSB) #define GTYE3_CH_CLK_COR_SEQ_1_ENABLE_ADDR 0x0022 #define GTYE3_CH_CLK_COR_SEQ_1_ENABLE_MSB 15 #define GTYE3_CH_CLK_COR_SEQ_1_ENABLE_LSB 12 #define GTYE3_CH_CLK_COR_SEQ_1_ENABLE_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_1_ENABLE_MSB, GTYE3_CH_CLK_COR_SEQ_1_ENABLE_LSB) #define GTYE3_CH_CLK_COR_SEQ_2_1_ADDR 0x0022 #define GTYE3_CH_CLK_COR_SEQ_2_1_MSB 9 #define GTYE3_CH_CLK_COR_SEQ_2_1_LSB 0 #define GTYE3_CH_CLK_COR_SEQ_2_1_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_2_1_MSB, GTYE3_CH_CLK_COR_SEQ_2_1_LSB) #define GTYE3_CH_CLK_COR_SEQ_2_2_ADDR 0x0023 #define GTYE3_CH_CLK_COR_SEQ_2_2_MSB 9 #define GTYE3_CH_CLK_COR_SEQ_2_2_LSB 0 #define GTYE3_CH_CLK_COR_SEQ_2_2_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_2_2_MSB, GTYE3_CH_CLK_COR_SEQ_2_2_LSB) #define GTYE3_CH_CLK_COR_SEQ_2_ENABLE_ADDR 0x0024 #define GTYE3_CH_CLK_COR_SEQ_2_ENABLE_MSB 15 #define GTYE3_CH_CLK_COR_SEQ_2_ENABLE_LSB 12 #define GTYE3_CH_CLK_COR_SEQ_2_ENABLE_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_2_ENABLE_MSB, GTYE3_CH_CLK_COR_SEQ_2_ENABLE_LSB) #define GTYE3_CH_CLK_COR_SEQ_2_USE_ADDR 0x0024 #define GTYE3_CH_CLK_COR_SEQ_2_USE_MSB 11 #define GTYE3_CH_CLK_COR_SEQ_2_USE_LSB 11 #define GTYE3_CH_CLK_COR_SEQ_2_USE_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_2_USE_MSB, GTYE3_CH_CLK_COR_SEQ_2_USE_LSB) #define GTYE3_CH_CLK_CORRECT_USE_ADDR 0x0024 #define GTYE3_CH_CLK_CORRECT_USE_MSB 10 #define GTYE3_CH_CLK_CORRECT_USE_LSB 10 #define GTYE3_CH_CLK_CORRECT_USE_MASK BIT_MASK(GTYE3_CH_CLK_CORRECT_USE_MSB, GTYE3_CH_CLK_CORRECT_USE_LSB) #define GTYE3_CH_CLK_COR_SEQ_2_3_ADDR 0x0024 #define GTYE3_CH_CLK_COR_SEQ_2_3_MSB 9 #define GTYE3_CH_CLK_COR_SEQ_2_3_LSB 0 #define GTYE3_CH_CLK_COR_SEQ_2_3_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_2_3_MSB, GTYE3_CH_CLK_COR_SEQ_2_3_LSB) #define GTYE3_CH_CLK_COR_SEQ_2_4_ADDR 0x0025 #define GTYE3_CH_CLK_COR_SEQ_2_4_MSB 9 #define GTYE3_CH_CLK_COR_SEQ_2_4_LSB 0 #define GTYE3_CH_CLK_COR_SEQ_2_4_MASK BIT_MASK(GTYE3_CH_CLK_COR_SEQ_2_4_MSB, GTYE3_CH_CLK_COR_SEQ_2_4_LSB) #define GTYE3_CH_RXDFE_HE_CFG0_ADDR 0x0026 #define GTYE3_CH_RXDFE_HE_CFG0_MSB 15 #define GTYE3_CH_RXDFE_HE_CFG0_LSB 0 #define GTYE3_CH_RXDFE_HE_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_HE_CFG0_MSB, GTYE3_CH_RXDFE_HE_CFG0_LSB) #define GTYE3_CH_ALIGN_COMMA_WORD_ADDR 0x0027 #define GTYE3_CH_ALIGN_COMMA_WORD_MSB 15 #define GTYE3_CH_ALIGN_COMMA_WORD_LSB 13 #define GTYE3_CH_ALIGN_COMMA_WORD_MASK BIT_MASK(GTYE3_CH_ALIGN_COMMA_WORD_MSB, GTYE3_CH_ALIGN_COMMA_WORD_LSB) #define GTYE3_CH_ALIGN_COMMA_DOUBLE_ADDR 0x0027 #define GTYE3_CH_ALIGN_COMMA_DOUBLE_MSB 12 #define GTYE3_CH_ALIGN_COMMA_DOUBLE_LSB 12 #define GTYE3_CH_ALIGN_COMMA_DOUBLE_MASK BIT_MASK(GTYE3_CH_ALIGN_COMMA_DOUBLE_MSB, GTYE3_CH_ALIGN_COMMA_DOUBLE_LSB) #define GTYE3_CH_SHOW_REALIGN_COMMA_ADDR 0x0027 #define GTYE3_CH_SHOW_REALIGN_COMMA_MSB 11 #define GTYE3_CH_SHOW_REALIGN_COMMA_LSB 11 #define GTYE3_CH_SHOW_REALIGN_COMMA_MASK BIT_MASK(GTYE3_CH_SHOW_REALIGN_COMMA_MSB, GTYE3_CH_SHOW_REALIGN_COMMA_LSB) #define GTYE3_CH_ALIGN_COMMA_ENABLE_ADDR 0x0027 #define GTYE3_CH_ALIGN_COMMA_ENABLE_MSB 9 #define GTYE3_CH_ALIGN_COMMA_ENABLE_LSB 0 #define GTYE3_CH_ALIGN_COMMA_ENABLE_MASK BIT_MASK(GTYE3_CH_ALIGN_COMMA_ENABLE_MSB, GTYE3_CH_ALIGN_COMMA_ENABLE_LSB) #define GTYE3_CH_CPLL_FBDIV_ADDR 0x0028 #define GTYE3_CH_CPLL_FBDIV_MSB 15 #define GTYE3_CH_CPLL_FBDIV_LSB 8 #define GTYE3_CH_CPLL_FBDIV_MASK BIT_MASK(GTYE3_CH_CPLL_FBDIV_MSB, GTYE3_CH_CPLL_FBDIV_LSB) #define GTYE3_CH_CPLL_FBDIV_1 16 #define GTYE3_CH_CPLL_FBDIV_2 0 #define GTYE3_CH_CPLL_FBDIV_3 1 #define GTYE3_CH_CPLL_FBDIV_4 2 #define GTYE3_CH_CPLL_FBDIV_5 3 #define GTYE3_CH_CPLL_FBDIV_45_ADDR 0x0028 #define GTYE3_CH_CPLL_FBDIV_45_MSB 7 #define GTYE3_CH_CPLL_FBDIV_45_LSB 7 #define GTYE3_CH_CPLL_FBDIV_45_MASK BIT_MASK(GTYE3_CH_CPLL_FBDIV_45_MSB, GTYE3_CH_CPLL_FBDIV_45_LSB) #define GTYE3_CH_CPLL_FBDIV_45_4 0 #define GTYE3_CH_CPLL_FBDIV_45_5 1 #define GTYE3_CH_CPLL_LOCK_CFG_ADDR 0x0029 #define GTYE3_CH_CPLL_LOCK_CFG_MSB 15 #define GTYE3_CH_CPLL_LOCK_CFG_LSB 0 #define GTYE3_CH_CPLL_LOCK_CFG_MASK BIT_MASK(GTYE3_CH_CPLL_LOCK_CFG_MSB, GTYE3_CH_CPLL_LOCK_CFG_LSB) #define GTYE3_CH_CPLL_REFCLK_DIV_ADDR 0x002A #define GTYE3_CH_CPLL_REFCLK_DIV_MSB 15 #define GTYE3_CH_CPLL_REFCLK_DIV_LSB 11 #define GTYE3_CH_CPLL_REFCLK_DIV_MASK BIT_MASK(GTYE3_CH_CPLL_REFCLK_DIV_MSB, GTYE3_CH_CPLL_REFCLK_DIV_LSB) #define GTYE3_CH_CPLL_REFCLK_DIV_1 16 #define GTYE3_CH_CPLL_REFCLK_DIV_2 0 #define GTYE3_CH_CPLL_IPS_EN_ADDR 0x002A #define GTYE3_CH_CPLL_IPS_EN_MSB 10 #define GTYE3_CH_CPLL_IPS_EN_LSB 10 #define GTYE3_CH_CPLL_IPS_EN_MASK BIT_MASK(GTYE3_CH_CPLL_IPS_EN_MSB, GTYE3_CH_CPLL_IPS_EN_LSB) #define GTYE3_CH_CPLL_IPS_REFCLK_SEL_ADDR 0x002A #define GTYE3_CH_CPLL_IPS_REFCLK_SEL_MSB 9 #define GTYE3_CH_CPLL_IPS_REFCLK_SEL_LSB 7 #define GTYE3_CH_CPLL_IPS_REFCLK_SEL_MASK BIT_MASK(GTYE3_CH_CPLL_IPS_REFCLK_SEL_MSB, GTYE3_CH_CPLL_IPS_REFCLK_SEL_LSB) #define GTYE3_CH_SATA_CPLL_CFG_ADDR 0x002A #define GTYE3_CH_SATA_CPLL_CFG_MSB 6 #define GTYE3_CH_SATA_CPLL_CFG_LSB 5 #define GTYE3_CH_SATA_CPLL_CFG_MASK BIT_MASK(GTYE3_CH_SATA_CPLL_CFG_MSB, GTYE3_CH_SATA_CPLL_CFG_LSB) #define GTYE3_CH_SATA_CPLL_CFG_VCO_3000MHZ 0 #define GTYE3_CH_SATA_CPLL_CFG_VCO_1500MHZ 1 #define GTYE3_CH_SATA_CPLL_CFG_VCO_750MHZ 2 #define GTYE3_CH_A_TXDIFFCTRL_ADDR 0x002A #define GTYE3_CH_A_TXDIFFCTRL_MSB 4 #define GTYE3_CH_A_TXDIFFCTRL_LSB 0 #define GTYE3_CH_A_TXDIFFCTRL_MASK BIT_MASK(GTYE3_CH_A_TXDIFFCTRL_MSB, GTYE3_CH_A_TXDIFFCTRL_LSB) #define GTYE3_CH_CPLL_INIT_CFG0_ADDR 0x002B #define GTYE3_CH_CPLL_INIT_CFG0_MSB 15 #define GTYE3_CH_CPLL_INIT_CFG0_LSB 0 #define GTYE3_CH_CPLL_INIT_CFG0_MASK BIT_MASK(GTYE3_CH_CPLL_INIT_CFG0_MSB, GTYE3_CH_CPLL_INIT_CFG0_LSB) #define GTYE3_CH_DEC_PCOMMA_DETECT_ADDR 0x002C #define GTYE3_CH_DEC_PCOMMA_DETECT_MSB 15 #define GTYE3_CH_DEC_PCOMMA_DETECT_LSB 15 #define GTYE3_CH_DEC_PCOMMA_DETECT_MASK BIT_MASK(GTYE3_CH_DEC_PCOMMA_DETECT_MSB, GTYE3_CH_DEC_PCOMMA_DETECT_LSB) #define GTYE3_CH_TX_DIVRESET_TIME_ADDR 0x002C #define GTYE3_CH_TX_DIVRESET_TIME_MSB 11 #define GTYE3_CH_TX_DIVRESET_TIME_LSB 7 #define GTYE3_CH_TX_DIVRESET_TIME_MASK BIT_MASK(GTYE3_CH_TX_DIVRESET_TIME_MSB, GTYE3_CH_TX_DIVRESET_TIME_LSB) #define GTYE3_CH_RX_DIVRESET_TIME_ADDR 0x002C #define GTYE3_CH_RX_DIVRESET_TIME_MSB 6 #define GTYE3_CH_RX_DIVRESET_TIME_LSB 2 #define GTYE3_CH_RX_DIVRESET_TIME_MASK BIT_MASK(GTYE3_CH_RX_DIVRESET_TIME_MSB, GTYE3_CH_RX_DIVRESET_TIME_LSB) #define GTYE3_CH_A_TXPROGDIVRESET_ADDR 0x002C #define GTYE3_CH_A_TXPROGDIVRESET_MSB 1 #define GTYE3_CH_A_TXPROGDIVRESET_LSB 1 #define GTYE3_CH_A_TXPROGDIVRESET_MASK BIT_MASK(GTYE3_CH_A_TXPROGDIVRESET_MSB, GTYE3_CH_A_TXPROGDIVRESET_LSB) #define GTYE3_CH_A_RXPROGDIVRESET_ADDR 0x002C #define GTYE3_CH_A_RXPROGDIVRESET_MSB 0 #define GTYE3_CH_A_RXPROGDIVRESET_LSB 0 #define GTYE3_CH_A_RXPROGDIVRESET_MASK BIT_MASK(GTYE3_CH_A_RXPROGDIVRESET_MSB, GTYE3_CH_A_RXPROGDIVRESET_LSB) #define GTYE3_CH_RXCDR_LOCK_CFG1_ADDR 0x002D #define GTYE3_CH_RXCDR_LOCK_CFG1_MSB 15 #define GTYE3_CH_RXCDR_LOCK_CFG1_LSB 0 #define GTYE3_CH_RXCDR_LOCK_CFG1_MASK BIT_MASK(GTYE3_CH_RXCDR_LOCK_CFG1_MSB, GTYE3_CH_RXCDR_LOCK_CFG1_LSB) #define GTYE3_CH_RXCFOK_CFG1_ADDR 0x002E #define GTYE3_CH_RXCFOK_CFG1_MSB 15 #define GTYE3_CH_RXCFOK_CFG1_LSB 0 #define GTYE3_CH_RXCFOK_CFG1_MASK BIT_MASK(GTYE3_CH_RXCFOK_CFG1_MSB, GTYE3_CH_RXCFOK_CFG1_LSB) #define GTYE3_CH_RXDFE_H2_CFG0_ADDR 0x002F #define GTYE3_CH_RXDFE_H2_CFG0_MSB 15 #define GTYE3_CH_RXDFE_H2_CFG0_LSB 0 #define GTYE3_CH_RXDFE_H2_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_H2_CFG0_MSB, GTYE3_CH_RXDFE_H2_CFG0_LSB) #define GTYE3_CH_RXDFE_H2_CFG1_ADDR 0x0030 #define GTYE3_CH_RXDFE_H2_CFG1_MSB 15 #define GTYE3_CH_RXDFE_H2_CFG1_LSB 0 #define GTYE3_CH_RXDFE_H2_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_H2_CFG1_MSB, GTYE3_CH_RXDFE_H2_CFG1_LSB) #define GTYE3_CH_RXCFOK_CFG2_ADDR 0x0031 #define GTYE3_CH_RXCFOK_CFG2_MSB 15 #define GTYE3_CH_RXCFOK_CFG2_LSB 0 #define GTYE3_CH_RXCFOK_CFG2_MASK BIT_MASK(GTYE3_CH_RXCFOK_CFG2_MSB, GTYE3_CH_RXCFOK_CFG2_LSB) #define GTYE3_CH_RXLPM_CFG_ADDR 0x0032 #define GTYE3_CH_RXLPM_CFG_MSB 15 #define GTYE3_CH_RXLPM_CFG_LSB 0 #define GTYE3_CH_RXLPM_CFG_MASK BIT_MASK(GTYE3_CH_RXLPM_CFG_MSB, GTYE3_CH_RXLPM_CFG_LSB) #define GTYE3_CH_RXLPM_KH_CFG0_ADDR 0x0033 #define GTYE3_CH_RXLPM_KH_CFG0_MSB 15 #define GTYE3_CH_RXLPM_KH_CFG0_LSB 0 #define GTYE3_CH_RXLPM_KH_CFG0_MASK BIT_MASK(GTYE3_CH_RXLPM_KH_CFG0_MSB, GTYE3_CH_RXLPM_KH_CFG0_LSB) #define GTYE3_CH_RXLPM_KH_CFG1_ADDR 0x0034 #define GTYE3_CH_RXLPM_KH_CFG1_MSB 15 #define GTYE3_CH_RXLPM_KH_CFG1_LSB 0 #define GTYE3_CH_RXLPM_KH_CFG1_MASK BIT_MASK(GTYE3_CH_RXLPM_KH_CFG1_MSB, GTYE3_CH_RXLPM_KH_CFG1_LSB) #define GTYE3_CH_RXDFELPM_KL_CFG0_ADDR 0x0035 #define GTYE3_CH_RXDFELPM_KL_CFG0_MSB 15 #define GTYE3_CH_RXDFELPM_KL_CFG0_LSB 0 #define GTYE3_CH_RXDFELPM_KL_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFELPM_KL_CFG0_MSB, GTYE3_CH_RXDFELPM_KL_CFG0_LSB) #define GTYE3_CH_RXDFELPM_KL_CFG1_ADDR 0x0036 #define GTYE3_CH_RXDFELPM_KL_CFG1_MSB 15 #define GTYE3_CH_RXDFELPM_KL_CFG1_LSB 0 #define GTYE3_CH_RXDFELPM_KL_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFELPM_KL_CFG1_MSB, GTYE3_CH_RXDFELPM_KL_CFG1_LSB) #define GTYE3_CH_RXLPM_OS_CFG0_ADDR 0x0037 #define GTYE3_CH_RXLPM_OS_CFG0_MSB 15 #define GTYE3_CH_RXLPM_OS_CFG0_LSB 0 #define GTYE3_CH_RXLPM_OS_CFG0_MASK BIT_MASK(GTYE3_CH_RXLPM_OS_CFG0_MSB, GTYE3_CH_RXLPM_OS_CFG0_LSB) #define GTYE3_CH_RXLPM_OS_CFG1_ADDR 0x0038 #define GTYE3_CH_RXLPM_OS_CFG1_MSB 15 #define GTYE3_CH_RXLPM_OS_CFG1_LSB 0 #define GTYE3_CH_RXLPM_OS_CFG1_MASK BIT_MASK(GTYE3_CH_RXLPM_OS_CFG1_MSB, GTYE3_CH_RXLPM_OS_CFG1_LSB) #define GTYE3_CH_RXLPM_GC_CFG_ADDR 0x0039 #define GTYE3_CH_RXLPM_GC_CFG_MSB 15 #define GTYE3_CH_RXLPM_GC_CFG_LSB 0 #define GTYE3_CH_RXLPM_GC_CFG_MASK BIT_MASK(GTYE3_CH_RXLPM_GC_CFG_MSB, GTYE3_CH_RXLPM_GC_CFG_LSB) #define GTYE3_CH_DMONITOR_CFG1_ADDR 0x003A #define GTYE3_CH_DMONITOR_CFG1_MSB 15 #define GTYE3_CH_DMONITOR_CFG1_LSB 8 #define GTYE3_CH_DMONITOR_CFG1_MASK BIT_MASK(GTYE3_CH_DMONITOR_CFG1_MSB, GTYE3_CH_DMONITOR_CFG1_LSB) #define GTYE3_CH_ES_CONTROL_ADDR 0x003C #define GTYE3_CH_ES_CONTROL_MSB 15 #define GTYE3_CH_ES_CONTROL_LSB 10 #define GTYE3_CH_ES_CONTROL_MASK BIT_MASK(GTYE3_CH_ES_CONTROL_MSB, GTYE3_CH_ES_CONTROL_LSB) #define GTYE3_CH_ES_PRESCALE_ADDR 0x003C #define GTYE3_CH_ES_PRESCALE_MSB 4 #define GTYE3_CH_ES_PRESCALE_LSB 0 #define GTYE3_CH_ES_PRESCALE_MASK BIT_MASK(GTYE3_CH_ES_PRESCALE_MSB, GTYE3_CH_ES_PRESCALE_LSB) #define GTYE3_CH_ES_EYE_SCAN_EN_ADDR 0x003C #define GTYE3_CH_ES_EYE_SCAN_EN_MSB 8 #define GTYE3_CH_ES_EYE_SCAN_EN_LSB 8 #define GTYE3_CH_ES_EYE_SCAN_EN_MASK BIT_MASK(GTYE3_CH_ES_EYE_SCAN_EN_MSB, GTYE3_CH_ES_EYE_SCAN_EN_LSB) #define GTYE3_CH_ES_ERRDET_EN_ADDR 0x003C #define GTYE3_CH_ES_ERRDET_EN_MSB 9 #define GTYE3_CH_ES_ERRDET_EN_LSB 9 #define GTYE3_CH_ES_ERRDET_EN_MASK BIT_MASK(GTYE3_CH_ES_ERRDET_EN_MSB, GTYE3_CH_ES_ERRDET_EN_LSB) #define GTYE3_CH_RXDFE_HC_CFG0_ADDR 0x003D #define GTYE3_CH_RXDFE_HC_CFG0_MSB 15 #define GTYE3_CH_RXDFE_HC_CFG0_LSB 0 #define GTYE3_CH_RXDFE_HC_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_HC_CFG0_MSB, GTYE3_CH_RXDFE_HC_CFG0_LSB) #define GTYE3_CH_TX_PROGDIV_CFG_ADDR 0x003E #define GTYE3_CH_TX_PROGDIV_CFG_MSB 15 #define GTYE3_CH_TX_PROGDIV_CFG_LSB 0 #define GTYE3_CH_TX_PROGDIV_CFG_MASK BIT_MASK(GTYE3_CH_TX_PROGDIV_CFG_MSB, GTYE3_CH_TX_PROGDIV_CFG_LSB) #define GTYE3_CH_TX_PROGDIV_CFG_0 32768 #define GTYE3_CH_TX_PROGDIV_CFG_4 57744 #define GTYE3_CH_TX_PROGDIV_CFG_5 49648 #define GTYE3_CH_TX_PROGDIV_CFG_8 57728 #define GTYE3_CH_TX_PROGDIV_CFG_10 57760 #define GTYE3_CH_TX_PROGDIV_CFG_16 57730 #define GTYE3_CH_TX_PROGDIV_CFG_16P5 49672 #define GTYE3_CH_TX_PROGDIV_CFG_20 57762 #define GTYE3_CH_TX_PROGDIV_CFG_32 57734 #define GTYE3_CH_TX_PROGDIV_CFG_33 49800 #define GTYE3_CH_TX_PROGDIV_CFG_40 57766 #define GTYE3_CH_TX_PROGDIV_CFG_64 57742 #define GTYE3_CH_TX_PROGDIV_CFG_66 50056 #define GTYE3_CH_TX_PROGDIV_CFG_80 57743 #define GTYE3_CH_TX_PROGDIV_CFG_100 57775 #define GTYE3_CH_ES_QUALIFIER0_ADDR 0x003F #define GTYE3_CH_ES_QUALIFIER0_MSB 15 #define GTYE3_CH_ES_QUALIFIER0_LSB 0 #define GTYE3_CH_ES_QUALIFIER0_MASK BIT_MASK(GTYE3_CH_ES_QUALIFIER0_MSB, GTYE3_CH_ES_QUALIFIER0_LSB) #define GTYE3_CH_ES_QUALIFIER1_ADDR 0x0040 #define GTYE3_CH_ES_QUALIFIER1_MSB 15 #define GTYE3_CH_ES_QUALIFIER1_LSB 0 #define GTYE3_CH_ES_QUALIFIER1_MASK BIT_MASK(GTYE3_CH_ES_QUALIFIER1_MSB, GTYE3_CH_ES_QUALIFIER1_LSB) #define GTYE3_CH_ES_QUALIFIER2_ADDR 0x0041 #define GTYE3_CH_ES_QUALIFIER2_MSB 15 #define GTYE3_CH_ES_QUALIFIER2_LSB 0 #define GTYE3_CH_ES_QUALIFIER2_MASK BIT_MASK(GTYE3_CH_ES_QUALIFIER2_MSB, GTYE3_CH_ES_QUALIFIER2_LSB) #define GTYE3_CH_ES_QUALIFIER3_ADDR 0x0042 #define GTYE3_CH_ES_QUALIFIER3_MSB 15 #define GTYE3_CH_ES_QUALIFIER3_LSB 0 #define GTYE3_CH_ES_QUALIFIER3_MASK BIT_MASK(GTYE3_CH_ES_QUALIFIER3_MSB, GTYE3_CH_ES_QUALIFIER3_LSB) #define GTYE3_CH_ES_QUALIFIER4_ADDR 0x0043 #define GTYE3_CH_ES_QUALIFIER4_MSB 15 #define GTYE3_CH_ES_QUALIFIER4_LSB 0 #define GTYE3_CH_ES_QUALIFIER4_MASK BIT_MASK(GTYE3_CH_ES_QUALIFIER4_MSB, GTYE3_CH_ES_QUALIFIER4_LSB) #define GTYE3_CH_ES_QUAL_MASK0_ADDR 0x0044 #define GTYE3_CH_ES_QUAL_MASK0_MSB 15 #define GTYE3_CH_ES_QUAL_MASK0_LSB 0 #define GTYE3_CH_ES_QUAL_MASK0_MASK BIT_MASK(GTYE3_CH_ES_QUAL_MASK0_MSB, GTYE3_CH_ES_QUAL_MASK0_LSB) #define GTYE3_CH_ES_QUAL_MASK1_ADDR 0x0045 #define GTYE3_CH_ES_QUAL_MASK1_MSB 15 #define GTYE3_CH_ES_QUAL_MASK1_LSB 0 #define GTYE3_CH_ES_QUAL_MASK1_MASK BIT_MASK(GTYE3_CH_ES_QUAL_MASK1_MSB, GTYE3_CH_ES_QUAL_MASK1_LSB) #define GTYE3_CH_ES_QUAL_MASK2_ADDR 0x0046 #define GTYE3_CH_ES_QUAL_MASK2_MSB 15 #define GTYE3_CH_ES_QUAL_MASK2_LSB 0 #define GTYE3_CH_ES_QUAL_MASK2_MASK BIT_MASK(GTYE3_CH_ES_QUAL_MASK2_MSB, GTYE3_CH_ES_QUAL_MASK2_LSB) #define GTYE3_CH_ES_QUAL_MASK3_ADDR 0x0047 #define GTYE3_CH_ES_QUAL_MASK3_MSB 15 #define GTYE3_CH_ES_QUAL_MASK3_LSB 0 #define GTYE3_CH_ES_QUAL_MASK3_MASK BIT_MASK(GTYE3_CH_ES_QUAL_MASK3_MSB, GTYE3_CH_ES_QUAL_MASK3_LSB) #define GTYE3_CH_ES_QUAL_MASK4_ADDR 0x0048 #define GTYE3_CH_ES_QUAL_MASK4_MSB 15 #define GTYE3_CH_ES_QUAL_MASK4_LSB 0 #define GTYE3_CH_ES_QUAL_MASK4_MASK BIT_MASK(GTYE3_CH_ES_QUAL_MASK4_MSB, GTYE3_CH_ES_QUAL_MASK4_LSB) #define GTYE3_CH_ES_SDATA_MASK0_ADDR 0x0049 #define GTYE3_CH_ES_SDATA_MASK0_MSB 15 #define GTYE3_CH_ES_SDATA_MASK0_LSB 0 #define GTYE3_CH_ES_SDATA_MASK0_MASK BIT_MASK(GTYE3_CH_ES_SDATA_MASK0_MSB, GTYE3_CH_ES_SDATA_MASK0_LSB) #define GTYE3_CH_ES_SDATA_MASK1_ADDR 0x004A #define GTYE3_CH_ES_SDATA_MASK1_MSB 15 #define GTYE3_CH_ES_SDATA_MASK1_LSB 0 #define GTYE3_CH_ES_SDATA_MASK1_MASK BIT_MASK(GTYE3_CH_ES_SDATA_MASK1_MSB, GTYE3_CH_ES_SDATA_MASK1_LSB) #define GTYE3_CH_ES_SDATA_MASK2_ADDR 0x004B #define GTYE3_CH_ES_SDATA_MASK2_MSB 15 #define GTYE3_CH_ES_SDATA_MASK2_LSB 0 #define GTYE3_CH_ES_SDATA_MASK2_MASK BIT_MASK(GTYE3_CH_ES_SDATA_MASK2_MSB, GTYE3_CH_ES_SDATA_MASK2_LSB) #define GTYE3_CH_ES_SDATA_MASK3_ADDR 0x004C #define GTYE3_CH_ES_SDATA_MASK3_MSB 15 #define GTYE3_CH_ES_SDATA_MASK3_LSB 0 #define GTYE3_CH_ES_SDATA_MASK3_MASK BIT_MASK(GTYE3_CH_ES_SDATA_MASK3_MSB, GTYE3_CH_ES_SDATA_MASK3_LSB) #define GTYE3_CH_ES_SDATA_MASK4_ADDR 0x004D #define GTYE3_CH_ES_SDATA_MASK4_MSB 15 #define GTYE3_CH_ES_SDATA_MASK4_LSB 0 #define GTYE3_CH_ES_SDATA_MASK4_MASK BIT_MASK(GTYE3_CH_ES_SDATA_MASK4_MSB, GTYE3_CH_ES_SDATA_MASK4_LSB) #define GTYE3_CH_FTS_LANE_DESKEW_EN_ADDR 0x004E #define GTYE3_CH_FTS_LANE_DESKEW_EN_MSB 4 #define GTYE3_CH_FTS_LANE_DESKEW_EN_LSB 4 #define GTYE3_CH_FTS_LANE_DESKEW_EN_MASK BIT_MASK(GTYE3_CH_FTS_LANE_DESKEW_EN_MSB, GTYE3_CH_FTS_LANE_DESKEW_EN_LSB) #define GTYE3_CH_FTS_DESKEW_SEQ_ENABLE_ADDR 0x004E #define GTYE3_CH_FTS_DESKEW_SEQ_ENABLE_MSB 3 #define GTYE3_CH_FTS_DESKEW_SEQ_ENABLE_LSB 0 #define GTYE3_CH_FTS_DESKEW_SEQ_ENABLE_MASK BIT_MASK(GTYE3_CH_FTS_DESKEW_SEQ_ENABLE_MSB, GTYE3_CH_FTS_DESKEW_SEQ_ENABLE_LSB) #define GTYE3_CH_ES_HORZ_OFFSET_ADDR 0x004F #define GTYE3_CH_ES_HORZ_OFFSET_MSB 15 #define GTYE3_CH_ES_HORZ_OFFSET_LSB 4 #define GTYE3_CH_ES_HORZ_OFFSET_MASK BIT_MASK(GTYE3_CH_ES_HORZ_OFFSET_MSB, GTYE3_CH_ES_HORZ_OFFSET_LSB) #define GTYE3_CH_FTS_LANE_DESKEW_CFG_ADDR 0x004F #define GTYE3_CH_FTS_LANE_DESKEW_CFG_MSB 3 #define GTYE3_CH_FTS_LANE_DESKEW_CFG_LSB 0 #define GTYE3_CH_FTS_LANE_DESKEW_CFG_MASK BIT_MASK(GTYE3_CH_FTS_LANE_DESKEW_CFG_MSB, GTYE3_CH_FTS_LANE_DESKEW_CFG_LSB) #define GTYE3_CH_RXDFE_HC_CFG1_ADDR 0x0050 #define GTYE3_CH_RXDFE_HC_CFG1_MSB 15 #define GTYE3_CH_RXDFE_HC_CFG1_LSB 0 #define GTYE3_CH_RXDFE_HC_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_HC_CFG1_MSB, GTYE3_CH_RXDFE_HC_CFG1_LSB) #define GTYE3_CH_ES_PMA_CFG_ADDR 0x0051 #define GTYE3_CH_ES_PMA_CFG_MSB 9 #define GTYE3_CH_ES_PMA_CFG_LSB 0 #define GTYE3_CH_ES_PMA_CFG_MASK BIT_MASK(GTYE3_CH_ES_PMA_CFG_MSB, GTYE3_CH_ES_PMA_CFG_LSB) #define GTYE3_CH_RX_EN_HI_LR_ADDR 0x0052 #define GTYE3_CH_RX_EN_HI_LR_MSB 10 #define GTYE3_CH_RX_EN_HI_LR_LSB 10 #define GTYE3_CH_RX_EN_HI_LR_MASK BIT_MASK(GTYE3_CH_RX_EN_HI_LR_MSB, GTYE3_CH_RX_EN_HI_LR_LSB) #define GTYE3_CH_RX_DFE_AGC_CFG1_ADDR 0x0052 #define GTYE3_CH_RX_DFE_AGC_CFG1_MSB 4 #define GTYE3_CH_RX_DFE_AGC_CFG1_LSB 2 #define GTYE3_CH_RX_DFE_AGC_CFG1_MASK BIT_MASK(GTYE3_CH_RX_DFE_AGC_CFG1_MSB, GTYE3_CH_RX_DFE_AGC_CFG1_LSB) #define GTYE3_CH_RX_DFE_AGC_CFG0_ADDR 0x0052 #define GTYE3_CH_RX_DFE_AGC_CFG0_MSB 1 #define GTYE3_CH_RX_DFE_AGC_CFG0_LSB 0 #define GTYE3_CH_RX_DFE_AGC_CFG0_MASK BIT_MASK(GTYE3_CH_RX_DFE_AGC_CFG0_MSB, GTYE3_CH_RX_DFE_AGC_CFG0_LSB) #define GTYE3_CH_RXDFE_CFG0_ADDR 0x0053 #define GTYE3_CH_RXDFE_CFG0_MSB 15 #define GTYE3_CH_RXDFE_CFG0_LSB 0 #define GTYE3_CH_RXDFE_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_CFG0_MSB, GTYE3_CH_RXDFE_CFG0_LSB) #define GTYE3_CH_RXDFE_CFG1_ADDR 0x0054 #define GTYE3_CH_RXDFE_CFG1_MSB 15 #define GTYE3_CH_RXDFE_CFG1_LSB 0 #define GTYE3_CH_RXDFE_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_CFG1_MSB, GTYE3_CH_RXDFE_CFG1_LSB) #define GTYE3_CH_LOCAL_MASTER_ADDR 0x0055 #define GTYE3_CH_LOCAL_MASTER_MSB 13 #define GTYE3_CH_LOCAL_MASTER_LSB 13 #define GTYE3_CH_LOCAL_MASTER_MASK BIT_MASK(GTYE3_CH_LOCAL_MASTER_MSB, GTYE3_CH_LOCAL_MASTER_LSB) #define GTYE3_CH_PCS_PCIE_EN_ADDR 0x0055 #define GTYE3_CH_PCS_PCIE_EN_MSB 12 #define GTYE3_CH_PCS_PCIE_EN_LSB 12 #define GTYE3_CH_PCS_PCIE_EN_MASK BIT_MASK(GTYE3_CH_PCS_PCIE_EN_MSB, GTYE3_CH_PCS_PCIE_EN_LSB) #define GTYE3_CH_ALIGN_MCOMMA_DET_ADDR 0x0055 #define GTYE3_CH_ALIGN_MCOMMA_DET_MSB 10 #define GTYE3_CH_ALIGN_MCOMMA_DET_LSB 10 #define GTYE3_CH_ALIGN_MCOMMA_DET_MASK BIT_MASK(GTYE3_CH_ALIGN_MCOMMA_DET_MSB, GTYE3_CH_ALIGN_MCOMMA_DET_LSB) #define GTYE3_CH_ALIGN_MCOMMA_VALUE_ADDR 0x0055 #define GTYE3_CH_ALIGN_MCOMMA_VALUE_MSB 9 #define GTYE3_CH_ALIGN_MCOMMA_VALUE_LSB 0 #define GTYE3_CH_ALIGN_MCOMMA_VALUE_MASK BIT_MASK(GTYE3_CH_ALIGN_MCOMMA_VALUE_MSB, GTYE3_CH_ALIGN_MCOMMA_VALUE_LSB) #define GTYE3_CH_ALIGN_PCOMMA_DET_ADDR 0x0056 #define GTYE3_CH_ALIGN_PCOMMA_DET_MSB 10 #define GTYE3_CH_ALIGN_PCOMMA_DET_LSB 10 #define GTYE3_CH_ALIGN_PCOMMA_DET_MASK BIT_MASK(GTYE3_CH_ALIGN_PCOMMA_DET_MSB, GTYE3_CH_ALIGN_PCOMMA_DET_LSB) #define GTYE3_CH_ALIGN_PCOMMA_VALUE_ADDR 0x0056 #define GTYE3_CH_ALIGN_PCOMMA_VALUE_MSB 9 #define GTYE3_CH_ALIGN_PCOMMA_VALUE_LSB 0 #define GTYE3_CH_ALIGN_PCOMMA_VALUE_MASK BIT_MASK(GTYE3_CH_ALIGN_PCOMMA_VALUE_MSB, GTYE3_CH_ALIGN_PCOMMA_VALUE_LSB) #define GTYE3_CH_TXDLY_LCFG_ADDR 0x0057 #define GTYE3_CH_TXDLY_LCFG_MSB 15 #define GTYE3_CH_TXDLY_LCFG_LSB 0 #define GTYE3_CH_TXDLY_LCFG_MASK BIT_MASK(GTYE3_CH_TXDLY_LCFG_MSB, GTYE3_CH_TXDLY_LCFG_LSB) #define GTYE3_CH_RXDFE_OS_CFG0_ADDR 0x0058 #define GTYE3_CH_RXDFE_OS_CFG0_MSB 15 #define GTYE3_CH_RXDFE_OS_CFG0_LSB 0 #define GTYE3_CH_RXDFE_OS_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_OS_CFG0_MSB, GTYE3_CH_RXDFE_OS_CFG0_LSB) #define GTYE3_CH_RXPHDLY_CFG_ADDR 0x0059 #define GTYE3_CH_RXPHDLY_CFG_MSB 15 #define GTYE3_CH_RXPHDLY_CFG_LSB 0 #define GTYE3_CH_RXPHDLY_CFG_MASK BIT_MASK(GTYE3_CH_RXPHDLY_CFG_MSB, GTYE3_CH_RXPHDLY_CFG_LSB) #define GTYE3_CH_RXDFE_OS_CFG1_ADDR 0x005A #define GTYE3_CH_RXDFE_OS_CFG1_MSB 15 #define GTYE3_CH_RXDFE_OS_CFG1_LSB 0 #define GTYE3_CH_RXDFE_OS_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_OS_CFG1_MSB, GTYE3_CH_RXDFE_OS_CFG1_LSB) #define GTYE3_CH_RXDLY_CFG_ADDR 0x005B #define GTYE3_CH_RXDLY_CFG_MSB 15 #define GTYE3_CH_RXDLY_CFG_LSB 0 #define GTYE3_CH_RXDLY_CFG_MASK BIT_MASK(GTYE3_CH_RXDLY_CFG_MSB, GTYE3_CH_RXDLY_CFG_LSB) #define GTYE3_CH_RXDLY_LCFG_ADDR 0x005C #define GTYE3_CH_RXDLY_LCFG_MSB 15 #define GTYE3_CH_RXDLY_LCFG_LSB 0 #define GTYE3_CH_RXDLY_LCFG_MASK BIT_MASK(GTYE3_CH_RXDLY_LCFG_MSB, GTYE3_CH_RXDLY_LCFG_LSB) #define GTYE3_CH_RXDFE_HF_CFG0_ADDR 0x005D #define GTYE3_CH_RXDFE_HF_CFG0_MSB 15 #define GTYE3_CH_RXDFE_HF_CFG0_LSB 0 #define GTYE3_CH_RXDFE_HF_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_HF_CFG0_MSB, GTYE3_CH_RXDFE_HF_CFG0_LSB) #define GTYE3_CH_RXDFE_HD_CFG0_ADDR 0x005E #define GTYE3_CH_RXDFE_HD_CFG0_MSB 15 #define GTYE3_CH_RXDFE_HD_CFG0_LSB 0 #define GTYE3_CH_RXDFE_HD_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_HD_CFG0_MSB, GTYE3_CH_RXDFE_HD_CFG0_LSB) #define GTYE3_CH_RX_BIAS_CFG0_ADDR 0x005F #define GTYE3_CH_RX_BIAS_CFG0_MSB 15 #define GTYE3_CH_RX_BIAS_CFG0_LSB 0 #define GTYE3_CH_RX_BIAS_CFG0_MASK BIT_MASK(GTYE3_CH_RX_BIAS_CFG0_MSB, GTYE3_CH_RX_BIAS_CFG0_LSB) #define GTYE3_CH_PCS_RSVD0_ADDR 0x0060 #define GTYE3_CH_PCS_RSVD0_MSB 15 #define GTYE3_CH_PCS_RSVD0_LSB 0 #define GTYE3_CH_PCS_RSVD0_MASK BIT_MASK(GTYE3_CH_PCS_RSVD0_MSB, GTYE3_CH_PCS_RSVD0_LSB) #define GTYE3_CH_RXPH_MONITOR_SEL_ADDR 0x0061 #define GTYE3_CH_RXPH_MONITOR_SEL_MSB 15 #define GTYE3_CH_RXPH_MONITOR_SEL_LSB 11 #define GTYE3_CH_RXPH_MONITOR_SEL_MASK BIT_MASK(GTYE3_CH_RXPH_MONITOR_SEL_MSB, GTYE3_CH_RXPH_MONITOR_SEL_LSB) #define GTYE3_CH_RX_CM_BUF_PD_ADDR 0x0061 #define GTYE3_CH_RX_CM_BUF_PD_MSB 10 #define GTYE3_CH_RX_CM_BUF_PD_LSB 10 #define GTYE3_CH_RX_CM_BUF_PD_MASK BIT_MASK(GTYE3_CH_RX_CM_BUF_PD_MSB, GTYE3_CH_RX_CM_BUF_PD_LSB) #define GTYE3_CH_RX_CM_BUF_CFG_ADDR 0x0061 #define GTYE3_CH_RX_CM_BUF_CFG_MSB 9 #define GTYE3_CH_RX_CM_BUF_CFG_LSB 6 #define GTYE3_CH_RX_CM_BUF_CFG_MASK BIT_MASK(GTYE3_CH_RX_CM_BUF_CFG_MSB, GTYE3_CH_RX_CM_BUF_CFG_LSB) #define GTYE3_CH_RX_CM_TRIM_ADDR 0x0061 #define GTYE3_CH_RX_CM_TRIM_MSB 5 #define GTYE3_CH_RX_CM_TRIM_LSB 2 #define GTYE3_CH_RX_CM_TRIM_MASK BIT_MASK(GTYE3_CH_RX_CM_TRIM_MSB, GTYE3_CH_RX_CM_TRIM_LSB) #define GTYE3_CH_RX_CM_SEL_ADDR 0x0061 #define GTYE3_CH_RX_CM_SEL_MSB 1 #define GTYE3_CH_RX_CM_SEL_LSB 0 #define GTYE3_CH_RX_CM_SEL_MASK BIT_MASK(GTYE3_CH_RX_CM_SEL_MSB, GTYE3_CH_RX_CM_SEL_LSB) #define GTYE3_CH_RX_SUM_IREF_TUNE_ADDR 0x0062 #define GTYE3_CH_RX_SUM_IREF_TUNE_MSB 12 #define GTYE3_CH_RX_SUM_IREF_TUNE_LSB 9 #define GTYE3_CH_RX_SUM_IREF_TUNE_MASK BIT_MASK(GTYE3_CH_RX_SUM_IREF_TUNE_MSB, GTYE3_CH_RX_SUM_IREF_TUNE_LSB) #define GTYE3_CH_RX_SUM_DFETAPREP_EN_ADDR 0x0062 #define GTYE3_CH_RX_SUM_DFETAPREP_EN_MSB 14 #define GTYE3_CH_RX_SUM_DFETAPREP_EN_LSB 14 #define GTYE3_CH_RX_SUM_DFETAPREP_EN_MASK BIT_MASK(GTYE3_CH_RX_SUM_DFETAPREP_EN_MSB, GTYE3_CH_RX_SUM_DFETAPREP_EN_LSB) #define GTYE3_CH_RX_SUM_VCM_OVWR_ADDR 0x0062 #define GTYE3_CH_RX_SUM_VCM_OVWR_MSB 13 #define GTYE3_CH_RX_SUM_VCM_OVWR_LSB 13 #define GTYE3_CH_RX_SUM_VCM_OVWR_MASK BIT_MASK(GTYE3_CH_RX_SUM_VCM_OVWR_MSB, GTYE3_CH_RX_SUM_VCM_OVWR_LSB) #define GTYE3_CH_RX_SUM_VCMTUNE_ADDR 0x0062 #define GTYE3_CH_RX_SUM_VCMTUNE_MSB 6 #define GTYE3_CH_RX_SUM_VCMTUNE_LSB 3 #define GTYE3_CH_RX_SUM_VCMTUNE_MASK BIT_MASK(GTYE3_CH_RX_SUM_VCMTUNE_MSB, GTYE3_CH_RX_SUM_VCMTUNE_LSB) #define GTYE3_CH_RX_SUM_VREF_TUNE_ADDR 0x0062 #define GTYE3_CH_RX_SUM_VREF_TUNE_MSB 2 #define GTYE3_CH_RX_SUM_VREF_TUNE_LSB 0 #define GTYE3_CH_RX_SUM_VREF_TUNE_MASK BIT_MASK(GTYE3_CH_RX_SUM_VREF_TUNE_MSB, GTYE3_CH_RX_SUM_VREF_TUNE_LSB) #define GTYE3_CH_CBCC_DATA_SOURCE_SEL_ADDR 0x0063 #define GTYE3_CH_CBCC_DATA_SOURCE_SEL_MSB 15 #define GTYE3_CH_CBCC_DATA_SOURCE_SEL_LSB 15 #define GTYE3_CH_CBCC_DATA_SOURCE_SEL_MASK BIT_MASK(GTYE3_CH_CBCC_DATA_SOURCE_SEL_MSB, GTYE3_CH_CBCC_DATA_SOURCE_SEL_LSB) #define GTYE3_CH_CBCC_DATA_SOURCE_SEL_ENCODED 0 #define GTYE3_CH_CBCC_DATA_SOURCE_SEL_DECODED 1 #define GTYE3_CH_OOB_PWRUP_ADDR 0x0063 #define GTYE3_CH_OOB_PWRUP_MSB 14 #define GTYE3_CH_OOB_PWRUP_LSB 14 #define GTYE3_CH_OOB_PWRUP_MASK BIT_MASK(GTYE3_CH_OOB_PWRUP_MSB, GTYE3_CH_OOB_PWRUP_LSB) #define GTYE3_CH_RXOOB_CFG_ADDR 0x0063 #define GTYE3_CH_RXOOB_CFG_MSB 13 #define GTYE3_CH_RXOOB_CFG_LSB 5 #define GTYE3_CH_RXOOB_CFG_MASK BIT_MASK(GTYE3_CH_RXOOB_CFG_MSB, GTYE3_CH_RXOOB_CFG_LSB) #define GTYE3_CH_RXOUT_DIV_ADDR 0x0063 #define GTYE3_CH_RXOUT_DIV_MSB 2 #define GTYE3_CH_RXOUT_DIV_LSB 0 #define GTYE3_CH_RXOUT_DIV_MASK BIT_MASK(GTYE3_CH_RXOUT_DIV_MSB, GTYE3_CH_RXOUT_DIV_LSB) #define GTYE3_CH_RXOUT_DIV_1 0 #define GTYE3_CH_RXOUT_DIV_2 1 #define GTYE3_CH_RXOUT_DIV_4 2 #define GTYE3_CH_RXOUT_DIV_8 3 #define GTYE3_CH_RXOUT_DIV_16 4 #define GTYE3_CH_RXOUT_DIV_32 5 #define GTYE3_CH_RX_SIG_VALID_DLY_ADDR 0x0064 #define GTYE3_CH_RX_SIG_VALID_DLY_MSB 15 #define GTYE3_CH_RX_SIG_VALID_DLY_LSB 11 #define GTYE3_CH_RX_SIG_VALID_DLY_MASK BIT_MASK(GTYE3_CH_RX_SIG_VALID_DLY_MSB, GTYE3_CH_RX_SIG_VALID_DLY_LSB) #define GTYE3_CH_RXSLIDE_MODE_ADDR 0x0064 #define GTYE3_CH_RXSLIDE_MODE_MSB 10 #define GTYE3_CH_RXSLIDE_MODE_LSB 9 #define GTYE3_CH_RXSLIDE_MODE_MASK BIT_MASK(GTYE3_CH_RXSLIDE_MODE_MSB, GTYE3_CH_RXSLIDE_MODE_LSB) #define GTYE3_CH_RXSLIDE_MODE_OFF 0 #define GTYE3_CH_RXSLIDE_MODE_AUTO 1 #define GTYE3_CH_RXSLIDE_MODE_PCS 2 #define GTYE3_CH_RXSLIDE_MODE_PMA 3 #define GTYE3_CH_RXPRBS_ERR_LOOPBACK_ADDR 0x0064 #define GTYE3_CH_RXPRBS_ERR_LOOPBACK_MSB 8 #define GTYE3_CH_RXPRBS_ERR_LOOPBACK_LSB 8 #define GTYE3_CH_RXPRBS_ERR_LOOPBACK_MASK BIT_MASK(GTYE3_CH_RXPRBS_ERR_LOOPBACK_MSB, GTYE3_CH_RXPRBS_ERR_LOOPBACK_LSB) #define GTYE3_CH_RXSLIDE_AUTO_WAIT_ADDR 0x0064 #define GTYE3_CH_RXSLIDE_AUTO_WAIT_MSB 7 #define GTYE3_CH_RXSLIDE_AUTO_WAIT_LSB 4 #define GTYE3_CH_RXSLIDE_AUTO_WAIT_MASK BIT_MASK(GTYE3_CH_RXSLIDE_AUTO_WAIT_MSB, GTYE3_CH_RXSLIDE_AUTO_WAIT_LSB) #define GTYE3_CH_RXBUF_EN_ADDR 0x0064 #define GTYE3_CH_RXBUF_EN_MSB 3 #define GTYE3_CH_RXBUF_EN_LSB 3 #define GTYE3_CH_RXBUF_EN_MASK BIT_MASK(GTYE3_CH_RXBUF_EN_MSB, GTYE3_CH_RXBUF_EN_LSB) #define GTYE3_CH_RX_XCLK_SEL_ADDR 0x0064 #define GTYE3_CH_RX_XCLK_SEL_MSB 2 #define GTYE3_CH_RX_XCLK_SEL_LSB 1 #define GTYE3_CH_RX_XCLK_SEL_MASK BIT_MASK(GTYE3_CH_RX_XCLK_SEL_MSB, GTYE3_CH_RX_XCLK_SEL_LSB) #define GTYE3_CH_RX_XCLK_SEL_RXDES 0 #define GTYE3_CH_RX_XCLK_SEL_RXUSR 1 #define GTYE3_CH_RX_XCLK_SEL_RXPMA 2 #define GTYE3_CH_RXGEARBOX_EN_ADDR 0x0064 #define GTYE3_CH_RXGEARBOX_EN_MSB 0 #define GTYE3_CH_RXGEARBOX_EN_LSB 0 #define GTYE3_CH_RXGEARBOX_EN_MASK BIT_MASK(GTYE3_CH_RXGEARBOX_EN_MSB, GTYE3_CH_RXGEARBOX_EN_LSB) #define GTYE3_CH_RXBUF_THRESH_OVFLW_ADDR 0x0065 #define GTYE3_CH_RXBUF_THRESH_OVFLW_MSB 15 #define GTYE3_CH_RXBUF_THRESH_OVFLW_LSB 10 #define GTYE3_CH_RXBUF_THRESH_OVFLW_MASK BIT_MASK(GTYE3_CH_RXBUF_THRESH_OVFLW_MSB, GTYE3_CH_RXBUF_THRESH_OVFLW_LSB) #define GTYE3_CH_DMONITOR_CFG0_ADDR 0x0065 #define GTYE3_CH_DMONITOR_CFG0_MSB 9 #define GTYE3_CH_DMONITOR_CFG0_LSB 0 #define GTYE3_CH_DMONITOR_CFG0_MASK BIT_MASK(GTYE3_CH_DMONITOR_CFG0_MSB, GTYE3_CH_DMONITOR_CFG0_LSB) #define GTYE3_CH_RXBUF_THRESH_OVRD_ADDR 0x0066 #define GTYE3_CH_RXBUF_THRESH_OVRD_MSB 15 #define GTYE3_CH_RXBUF_THRESH_OVRD_LSB 15 #define GTYE3_CH_RXBUF_THRESH_OVRD_MASK BIT_MASK(GTYE3_CH_RXBUF_THRESH_OVRD_MSB, GTYE3_CH_RXBUF_THRESH_OVRD_LSB) #define GTYE3_CH_RXBUF_RESET_ON_COMMAALIGN_ADDR 0x0066 #define GTYE3_CH_RXBUF_RESET_ON_COMMAALIGN_MSB 14 #define GTYE3_CH_RXBUF_RESET_ON_COMMAALIGN_LSB 14 #define GTYE3_CH_RXBUF_RESET_ON_COMMAALIGN_MASK BIT_MASK(GTYE3_CH_RXBUF_RESET_ON_COMMAALIGN_MSB, GTYE3_CH_RXBUF_RESET_ON_COMMAALIGN_LSB) #define GTYE3_CH_RXBUF_RESET_ON_RATE_CHANGE_ADDR 0x0066 #define GTYE3_CH_RXBUF_RESET_ON_RATE_CHANGE_MSB 13 #define GTYE3_CH_RXBUF_RESET_ON_RATE_CHANGE_LSB 13 #define GTYE3_CH_RXBUF_RESET_ON_RATE_CHANGE_MASK BIT_MASK(GTYE3_CH_RXBUF_RESET_ON_RATE_CHANGE_MSB, GTYE3_CH_RXBUF_RESET_ON_RATE_CHANGE_LSB) #define GTYE3_CH_RXBUF_RESET_ON_CB_CHANGE_ADDR 0x0066 #define GTYE3_CH_RXBUF_RESET_ON_CB_CHANGE_MSB 12 #define GTYE3_CH_RXBUF_RESET_ON_CB_CHANGE_LSB 12 #define GTYE3_CH_RXBUF_RESET_ON_CB_CHANGE_MASK BIT_MASK(GTYE3_CH_RXBUF_RESET_ON_CB_CHANGE_MSB, GTYE3_CH_RXBUF_RESET_ON_CB_CHANGE_LSB) #define GTYE3_CH_RXBUF_THRESH_UNDFLW_ADDR 0x0066 #define GTYE3_CH_RXBUF_THRESH_UNDFLW_MSB 11 #define GTYE3_CH_RXBUF_THRESH_UNDFLW_LSB 6 #define GTYE3_CH_RXBUF_THRESH_UNDFLW_MASK BIT_MASK(GTYE3_CH_RXBUF_THRESH_UNDFLW_MSB, GTYE3_CH_RXBUF_THRESH_UNDFLW_LSB) #define GTYE3_CH_RX_CLKMUX_EN_ADDR 0x0066 #define GTYE3_CH_RX_CLKMUX_EN_MSB 5 #define GTYE3_CH_RX_CLKMUX_EN_LSB 5 #define GTYE3_CH_RX_CLKMUX_EN_MASK BIT_MASK(GTYE3_CH_RX_CLKMUX_EN_MSB, GTYE3_CH_RX_CLKMUX_EN_LSB) #define GTYE3_CH_RX_DISPERR_SEQ_MATCH_ADDR 0x0066 #define GTYE3_CH_RX_DISPERR_SEQ_MATCH_MSB 4 #define GTYE3_CH_RX_DISPERR_SEQ_MATCH_LSB 4 #define GTYE3_CH_RX_DISPERR_SEQ_MATCH_MASK BIT_MASK(GTYE3_CH_RX_DISPERR_SEQ_MATCH_MSB, GTYE3_CH_RX_DISPERR_SEQ_MATCH_LSB) #define GTYE3_CH_RX_WIDEMODE_CDR_ADDR 0x0066 #define GTYE3_CH_RX_WIDEMODE_CDR_MSB 3 #define GTYE3_CH_RX_WIDEMODE_CDR_LSB 2 #define GTYE3_CH_RX_WIDEMODE_CDR_MASK BIT_MASK(GTYE3_CH_RX_WIDEMODE_CDR_MSB, GTYE3_CH_RX_WIDEMODE_CDR_LSB) #define GTYE3_CH_RX_INT_DATAWIDTH_ADDR 0x0066 #define GTYE3_CH_RX_INT_DATAWIDTH_MSB 1 #define GTYE3_CH_RX_INT_DATAWIDTH_LSB 0 #define GTYE3_CH_RX_INT_DATAWIDTH_MASK BIT_MASK(GTYE3_CH_RX_INT_DATAWIDTH_MSB, GTYE3_CH_RX_INT_DATAWIDTH_LSB) #define GTYE3_CH_RXBUF_EIDLE_HI_CNT_ADDR 0x0067 #define GTYE3_CH_RXBUF_EIDLE_HI_CNT_MSB 15 #define GTYE3_CH_RXBUF_EIDLE_HI_CNT_LSB 12 #define GTYE3_CH_RXBUF_EIDLE_HI_CNT_MASK BIT_MASK(GTYE3_CH_RXBUF_EIDLE_HI_CNT_MSB, GTYE3_CH_RXBUF_EIDLE_HI_CNT_LSB) #define GTYE3_CH_RXCDR_HOLD_DURING_EIDLE_ADDR 0x0067 #define GTYE3_CH_RXCDR_HOLD_DURING_EIDLE_MSB 11 #define GTYE3_CH_RXCDR_HOLD_DURING_EIDLE_LSB 11 #define GTYE3_CH_RXCDR_HOLD_DURING_EIDLE_MASK BIT_MASK(GTYE3_CH_RXCDR_HOLD_DURING_EIDLE_MSB, GTYE3_CH_RXCDR_HOLD_DURING_EIDLE_LSB) #define GTYE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_ADDR 0x0067 #define GTYE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_MSB 10 #define GTYE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_LSB 10 #define GTYE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_MASK BIT_MASK(GTYE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_MSB, GTYE3_CH_RX_DFE_LPM_HOLD_DURING_EIDLE_LSB) #define GTYE3_CH_RXBUF_EIDLE_LO_CNT_ADDR 0x0067 #define GTYE3_CH_RXBUF_EIDLE_LO_CNT_MSB 7 #define GTYE3_CH_RXBUF_EIDLE_LO_CNT_LSB 4 #define GTYE3_CH_RXBUF_EIDLE_LO_CNT_MASK BIT_MASK(GTYE3_CH_RXBUF_EIDLE_LO_CNT_MSB, GTYE3_CH_RXBUF_EIDLE_LO_CNT_LSB) #define GTYE3_CH_RXBUF_RESET_ON_EIDLE_ADDR 0x0067 #define GTYE3_CH_RXBUF_RESET_ON_EIDLE_MSB 3 #define GTYE3_CH_RXBUF_RESET_ON_EIDLE_LSB 3 #define GTYE3_CH_RXBUF_RESET_ON_EIDLE_MASK BIT_MASK(GTYE3_CH_RXBUF_RESET_ON_EIDLE_MSB, GTYE3_CH_RXBUF_RESET_ON_EIDLE_LSB) #define GTYE3_CH_RXCDR_FR_RESET_ON_EIDLE_ADDR 0x0067 #define GTYE3_CH_RXCDR_FR_RESET_ON_EIDLE_MSB 2 #define GTYE3_CH_RXCDR_FR_RESET_ON_EIDLE_LSB 2 #define GTYE3_CH_RXCDR_FR_RESET_ON_EIDLE_MASK BIT_MASK(GTYE3_CH_RXCDR_FR_RESET_ON_EIDLE_MSB, GTYE3_CH_RXCDR_FR_RESET_ON_EIDLE_LSB) #define GTYE3_CH_RXCDR_PH_RESET_ON_EIDLE_ADDR 0x0067 #define GTYE3_CH_RXCDR_PH_RESET_ON_EIDLE_MSB 1 #define GTYE3_CH_RXCDR_PH_RESET_ON_EIDLE_LSB 1 #define GTYE3_CH_RXCDR_PH_RESET_ON_EIDLE_MASK BIT_MASK(GTYE3_CH_RXCDR_PH_RESET_ON_EIDLE_MSB, GTYE3_CH_RXCDR_PH_RESET_ON_EIDLE_LSB) #define GTYE3_CH_RXBUF_ADDR_MODE_ADDR 0x0067 #define GTYE3_CH_RXBUF_ADDR_MODE_MSB 0 #define GTYE3_CH_RXBUF_ADDR_MODE_LSB 0 #define GTYE3_CH_RXBUF_ADDR_MODE_MASK BIT_MASK(GTYE3_CH_RXBUF_ADDR_MODE_MSB, GTYE3_CH_RXBUF_ADDR_MODE_LSB) #define GTYE3_CH_RXBUF_ADDR_MODE_FULL 0 #define GTYE3_CH_RXBUF_ADDR_MODE_FAST 1 #define GTYE3_CH_SATA_BURST_VAL_ADDR 0x0068 #define GTYE3_CH_SATA_BURST_VAL_MSB 15 #define GTYE3_CH_SATA_BURST_VAL_LSB 13 #define GTYE3_CH_SATA_BURST_VAL_MASK BIT_MASK(GTYE3_CH_SATA_BURST_VAL_MSB, GTYE3_CH_SATA_BURST_VAL_LSB) #define GTYE3_CH_SATA_BURST_SEQ_LEN_ADDR 0x0068 #define GTYE3_CH_SATA_BURST_SEQ_LEN_MSB 7 #define GTYE3_CH_SATA_BURST_SEQ_LEN_LSB 4 #define GTYE3_CH_SATA_BURST_SEQ_LEN_MASK BIT_MASK(GTYE3_CH_SATA_BURST_SEQ_LEN_MSB, GTYE3_CH_SATA_BURST_SEQ_LEN_LSB) #define GTYE3_CH_SATA_EIDLE_VAL_ADDR 0x0068 #define GTYE3_CH_SATA_EIDLE_VAL_MSB 2 #define GTYE3_CH_SATA_EIDLE_VAL_LSB 0 #define GTYE3_CH_SATA_EIDLE_VAL_MASK BIT_MASK(GTYE3_CH_SATA_EIDLE_VAL_MSB, GTYE3_CH_SATA_EIDLE_VAL_LSB) #define GTYE3_CH_SATA_MIN_BURST_ADDR 0x0069 #define GTYE3_CH_SATA_MIN_BURST_MSB 15 #define GTYE3_CH_SATA_MIN_BURST_LSB 10 #define GTYE3_CH_SATA_MIN_BURST_MASK BIT_MASK(GTYE3_CH_SATA_MIN_BURST_MSB, GTYE3_CH_SATA_MIN_BURST_LSB) #define GTYE3_CH_SAS_MIN_COM_ADDR 0x0069 #define GTYE3_CH_SAS_MIN_COM_MSB 6 #define GTYE3_CH_SAS_MIN_COM_LSB 1 #define GTYE3_CH_SAS_MIN_COM_MASK BIT_MASK(GTYE3_CH_SAS_MIN_COM_MSB, GTYE3_CH_SAS_MIN_COM_LSB) #define GTYE3_CH_SATA_MIN_INIT_ADDR 0x006A #define GTYE3_CH_SATA_MIN_INIT_MSB 15 #define GTYE3_CH_SATA_MIN_INIT_LSB 10 #define GTYE3_CH_SATA_MIN_INIT_MASK BIT_MASK(GTYE3_CH_SATA_MIN_INIT_MSB, GTYE3_CH_SATA_MIN_INIT_LSB) #define GTYE3_CH_SATA_MIN_WAKE_ADDR 0x006A #define GTYE3_CH_SATA_MIN_WAKE_MSB 6 #define GTYE3_CH_SATA_MIN_WAKE_LSB 1 #define GTYE3_CH_SATA_MIN_WAKE_MASK BIT_MASK(GTYE3_CH_SATA_MIN_WAKE_MSB, GTYE3_CH_SATA_MIN_WAKE_LSB) #define GTYE3_CH_SATA_MAX_BURST_ADDR 0x006B #define GTYE3_CH_SATA_MAX_BURST_MSB 15 #define GTYE3_CH_SATA_MAX_BURST_LSB 10 #define GTYE3_CH_SATA_MAX_BURST_MASK BIT_MASK(GTYE3_CH_SATA_MAX_BURST_MSB, GTYE3_CH_SATA_MAX_BURST_LSB) #define GTYE3_CH_SAS_MAX_COM_ADDR 0x006B #define GTYE3_CH_SAS_MAX_COM_MSB 6 #define GTYE3_CH_SAS_MAX_COM_LSB 0 #define GTYE3_CH_SAS_MAX_COM_MASK BIT_MASK(GTYE3_CH_SAS_MAX_COM_MSB, GTYE3_CH_SAS_MAX_COM_LSB) #define GTYE3_CH_SATA_MAX_INIT_ADDR 0x006C #define GTYE3_CH_SATA_MAX_INIT_MSB 15 #define GTYE3_CH_SATA_MAX_INIT_LSB 10 #define GTYE3_CH_SATA_MAX_INIT_MASK BIT_MASK(GTYE3_CH_SATA_MAX_INIT_MSB, GTYE3_CH_SATA_MAX_INIT_LSB) #define GTYE3_CH_SATA_MAX_WAKE_ADDR 0x006C #define GTYE3_CH_SATA_MAX_WAKE_MSB 6 #define GTYE3_CH_SATA_MAX_WAKE_LSB 1 #define GTYE3_CH_SATA_MAX_WAKE_MASK BIT_MASK(GTYE3_CH_SATA_MAX_WAKE_MSB, GTYE3_CH_SATA_MAX_WAKE_LSB) #define GTYE3_CH_RX_CLK25_DIV_ADDR 0x006D #define GTYE3_CH_RX_CLK25_DIV_MSB 7 #define GTYE3_CH_RX_CLK25_DIV_LSB 3 #define GTYE3_CH_RX_CLK25_DIV_MASK BIT_MASK(GTYE3_CH_RX_CLK25_DIV_MSB, GTYE3_CH_RX_CLK25_DIV_LSB) #define GTYE3_CH_TXPHDLY_CFG0_ADDR 0x006E #define GTYE3_CH_TXPHDLY_CFG0_MSB 15 #define GTYE3_CH_TXPHDLY_CFG0_LSB 0 #define GTYE3_CH_TXPHDLY_CFG0_MASK BIT_MASK(GTYE3_CH_TXPHDLY_CFG0_MSB, GTYE3_CH_TXPHDLY_CFG0_LSB) #define GTYE3_CH_TXPHDLY_CFG1_ADDR 0x006F #define GTYE3_CH_TXPHDLY_CFG1_MSB 15 #define GTYE3_CH_TXPHDLY_CFG1_LSB 0 #define GTYE3_CH_TXPHDLY_CFG1_MASK BIT_MASK(GTYE3_CH_TXPHDLY_CFG1_MSB, GTYE3_CH_TXPHDLY_CFG1_LSB) #define GTYE3_CH_TXDLY_CFG_ADDR 0x0070 #define GTYE3_CH_TXDLY_CFG_MSB 15 #define GTYE3_CH_TXDLY_CFG_LSB 0 #define GTYE3_CH_TXDLY_CFG_MASK BIT_MASK(GTYE3_CH_TXDLY_CFG_MSB, GTYE3_CH_TXDLY_CFG_LSB) #define GTYE3_CH_TXPH_MONITOR_SEL_ADDR 0x0071 #define GTYE3_CH_TXPH_MONITOR_SEL_MSB 6 #define GTYE3_CH_TXPH_MONITOR_SEL_LSB 2 #define GTYE3_CH_TXPH_MONITOR_SEL_MASK BIT_MASK(GTYE3_CH_TXPH_MONITOR_SEL_MSB, GTYE3_CH_TXPH_MONITOR_SEL_LSB) #define GTYE3_CH_TAPDLY_SET_TX_ADDR 0x0071 #define GTYE3_CH_TAPDLY_SET_TX_MSB 1 #define GTYE3_CH_TAPDLY_SET_TX_LSB 0 #define GTYE3_CH_TAPDLY_SET_TX_MASK BIT_MASK(GTYE3_CH_TAPDLY_SET_TX_MSB, GTYE3_CH_TAPDLY_SET_TX_LSB) #define GTYE3_CH_RXCDR_LOCK_CFG2_ADDR 0x0072 #define GTYE3_CH_RXCDR_LOCK_CFG2_MSB 15 #define GTYE3_CH_RXCDR_LOCK_CFG2_LSB 0 #define GTYE3_CH_RXCDR_LOCK_CFG2_MASK BIT_MASK(GTYE3_CH_RXCDR_LOCK_CFG2_MSB, GTYE3_CH_RXCDR_LOCK_CFG2_LSB) #define GTYE3_CH_TXPH_CFG_ADDR 0x0073 #define GTYE3_CH_TXPH_CFG_MSB 15 #define GTYE3_CH_TXPH_CFG_LSB 0 #define GTYE3_CH_TXPH_CFG_MASK BIT_MASK(GTYE3_CH_TXPH_CFG_MSB, GTYE3_CH_TXPH_CFG_LSB) #define GTYE3_CH_TERM_RCAL_CFG_ADDR 0x0074 #define GTYE3_CH_TERM_RCAL_CFG_MSB 14 #define GTYE3_CH_TERM_RCAL_CFG_LSB 0 #define GTYE3_CH_TERM_RCAL_CFG_MASK BIT_MASK(GTYE3_CH_TERM_RCAL_CFG_MSB, GTYE3_CH_TERM_RCAL_CFG_LSB) #define GTYE3_CH_RXDFE_HF_CFG1_ADDR 0x0075 #define GTYE3_CH_RXDFE_HF_CFG1_MSB 15 #define GTYE3_CH_RXDFE_HF_CFG1_LSB 0 #define GTYE3_CH_RXDFE_HF_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_HF_CFG1_MSB, GTYE3_CH_RXDFE_HF_CFG1_LSB) #define GTYE3_CH_PD_TRANS_TIME_FROM_P2_ADDR 0x0076 #define GTYE3_CH_PD_TRANS_TIME_FROM_P2_MSB 15 #define GTYE3_CH_PD_TRANS_TIME_FROM_P2_LSB 4 #define GTYE3_CH_PD_TRANS_TIME_FROM_P2_MASK BIT_MASK(GTYE3_CH_PD_TRANS_TIME_FROM_P2_MSB, GTYE3_CH_PD_TRANS_TIME_FROM_P2_LSB) #define GTYE3_CH_TERM_RCAL_OVRD_ADDR 0x0076 #define GTYE3_CH_TERM_RCAL_OVRD_MSB 3 #define GTYE3_CH_TERM_RCAL_OVRD_LSB 1 #define GTYE3_CH_TERM_RCAL_OVRD_MASK BIT_MASK(GTYE3_CH_TERM_RCAL_OVRD_MSB, GTYE3_CH_TERM_RCAL_OVRD_LSB) #define GTYE3_CH_PD_TRANS_TIME_NONE_P2_ADDR 0x0077 #define GTYE3_CH_PD_TRANS_TIME_NONE_P2_MSB 15 #define GTYE3_CH_PD_TRANS_TIME_NONE_P2_LSB 8 #define GTYE3_CH_PD_TRANS_TIME_NONE_P2_MASK BIT_MASK(GTYE3_CH_PD_TRANS_TIME_NONE_P2_MSB, GTYE3_CH_PD_TRANS_TIME_NONE_P2_LSB) #define GTYE3_CH_PD_TRANS_TIME_TO_P2_ADDR 0x0077 #define GTYE3_CH_PD_TRANS_TIME_TO_P2_MSB 7 #define GTYE3_CH_PD_TRANS_TIME_TO_P2_LSB 0 #define GTYE3_CH_PD_TRANS_TIME_TO_P2_MASK BIT_MASK(GTYE3_CH_PD_TRANS_TIME_TO_P2_MSB, GTYE3_CH_PD_TRANS_TIME_TO_P2_LSB) #define GTYE3_CH_TRANS_TIME_RATE_ADDR 0x0078 #define GTYE3_CH_TRANS_TIME_RATE_MSB 15 #define GTYE3_CH_TRANS_TIME_RATE_LSB 8 #define GTYE3_CH_TRANS_TIME_RATE_MASK BIT_MASK(GTYE3_CH_TRANS_TIME_RATE_MSB, GTYE3_CH_TRANS_TIME_RATE_LSB) #define GTYE3_CH_TST_RSV0_ADDR 0x0079 #define GTYE3_CH_TST_RSV0_MSB 15 #define GTYE3_CH_TST_RSV0_LSB 8 #define GTYE3_CH_TST_RSV0_MASK BIT_MASK(GTYE3_CH_TST_RSV0_MSB, GTYE3_CH_TST_RSV0_LSB) #define GTYE3_CH_TST_RSV1_ADDR 0x0079 #define GTYE3_CH_TST_RSV1_MSB 7 #define GTYE3_CH_TST_RSV1_LSB 0 #define GTYE3_CH_TST_RSV1_MASK BIT_MASK(GTYE3_CH_TST_RSV1_MSB, GTYE3_CH_TST_RSV1_LSB) #define GTYE3_CH_TX_CLK25_DIV_ADDR 0x007A #define GTYE3_CH_TX_CLK25_DIV_MSB 15 #define GTYE3_CH_TX_CLK25_DIV_LSB 11 #define GTYE3_CH_TX_CLK25_DIV_MASK BIT_MASK(GTYE3_CH_TX_CLK25_DIV_MSB, GTYE3_CH_TX_CLK25_DIV_LSB) #define GTYE3_CH_TX_XCLK_SEL_ADDR 0x007A #define GTYE3_CH_TX_XCLK_SEL_MSB 10 #define GTYE3_CH_TX_XCLK_SEL_LSB 10 #define GTYE3_CH_TX_XCLK_SEL_MASK BIT_MASK(GTYE3_CH_TX_XCLK_SEL_MSB, GTYE3_CH_TX_XCLK_SEL_LSB) #define GTYE3_CH_TX_XCLK_SEL_TXOUT 0 #define GTYE3_CH_TX_XCLK_SEL_TXUSR 1 #define GTYE3_CH_TX_DATA_WIDTH_ADDR 0x007A #define GTYE3_CH_TX_DATA_WIDTH_MSB 3 #define GTYE3_CH_TX_DATA_WIDTH_LSB 0 #define GTYE3_CH_TX_DATA_WIDTH_MASK BIT_MASK(GTYE3_CH_TX_DATA_WIDTH_MSB, GTYE3_CH_TX_DATA_WIDTH_LSB) #define GTYE3_CH_TX_DATA_WIDTH_16 2 #define GTYE3_CH_TX_DATA_WIDTH_20 3 #define GTYE3_CH_TX_DATA_WIDTH_32 4 #define GTYE3_CH_TX_DATA_WIDTH_40 5 #define GTYE3_CH_TX_DATA_WIDTH_64 6 #define GTYE3_CH_TX_DATA_WIDTH_80 7 #define GTYE3_CH_TX_DATA_WIDTH_128 8 #define GTYE3_CH_TX_DATA_WIDTH_160 9 #define GTYE3_CH_TX_DEEMPH0_ADDR 0x007B #define GTYE3_CH_TX_DEEMPH0_MSB 15 #define GTYE3_CH_TX_DEEMPH0_LSB 10 #define GTYE3_CH_TX_DEEMPH0_MASK BIT_MASK(GTYE3_CH_TX_DEEMPH0_MSB, GTYE3_CH_TX_DEEMPH0_LSB) #define GTYE3_CH_TX_DEEMPH1_ADDR 0x007B #define GTYE3_CH_TX_DEEMPH1_MSB 7 #define GTYE3_CH_TX_DEEMPH1_LSB 2 #define GTYE3_CH_TX_DEEMPH1_MASK BIT_MASK(GTYE3_CH_TX_DEEMPH1_MSB, GTYE3_CH_TX_DEEMPH1_LSB) #define GTYE3_CH_TX_MAINCURSOR_SEL_ADDR 0x007C #define GTYE3_CH_TX_MAINCURSOR_SEL_MSB 14 #define GTYE3_CH_TX_MAINCURSOR_SEL_LSB 14 #define GTYE3_CH_TX_MAINCURSOR_SEL_MASK BIT_MASK(GTYE3_CH_TX_MAINCURSOR_SEL_MSB, GTYE3_CH_TX_MAINCURSOR_SEL_LSB) #define GTYE3_CH_TXGEARBOX_EN_ADDR 0x007C #define GTYE3_CH_TXGEARBOX_EN_MSB 13 #define GTYE3_CH_TXGEARBOX_EN_LSB 13 #define GTYE3_CH_TXGEARBOX_EN_MASK BIT_MASK(GTYE3_CH_TXGEARBOX_EN_MSB, GTYE3_CH_TXGEARBOX_EN_LSB) #define GTYE3_CH_TXOUT_DIV_ADDR 0x007C #define GTYE3_CH_TXOUT_DIV_MSB 10 #define GTYE3_CH_TXOUT_DIV_LSB 8 #define GTYE3_CH_TXOUT_DIV_MASK BIT_MASK(GTYE3_CH_TXOUT_DIV_MSB, GTYE3_CH_TXOUT_DIV_LSB) #define GTYE3_CH_TXOUT_DIV_1 0 #define GTYE3_CH_TXOUT_DIV_2 1 #define GTYE3_CH_TXOUT_DIV_4 2 #define GTYE3_CH_TXOUT_DIV_8 3 #define GTYE3_CH_TXOUT_DIV_16 4 #define GTYE3_CH_TXOUT_DIV_32 5 #define GTYE3_CH_TXBUF_EN_ADDR 0x007C #define GTYE3_CH_TXBUF_EN_MSB 7 #define GTYE3_CH_TXBUF_EN_LSB 7 #define GTYE3_CH_TXBUF_EN_MASK BIT_MASK(GTYE3_CH_TXBUF_EN_MSB, GTYE3_CH_TXBUF_EN_LSB) #define GTYE3_CH_TXBUF_RESET_ON_RATE_CHANGE_ADDR 0x007C #define GTYE3_CH_TXBUF_RESET_ON_RATE_CHANGE_MSB 6 #define GTYE3_CH_TXBUF_RESET_ON_RATE_CHANGE_LSB 6 #define GTYE3_CH_TXBUF_RESET_ON_RATE_CHANGE_MASK BIT_MASK(GTYE3_CH_TXBUF_RESET_ON_RATE_CHANGE_MSB, GTYE3_CH_TXBUF_RESET_ON_RATE_CHANGE_LSB) #define GTYE3_CH_TX_RXDETECT_REF_ADDR 0x007C #define GTYE3_CH_TX_RXDETECT_REF_MSB 5 #define GTYE3_CH_TX_RXDETECT_REF_LSB 3 #define GTYE3_CH_TX_RXDETECT_REF_MASK BIT_MASK(GTYE3_CH_TX_RXDETECT_REF_MSB, GTYE3_CH_TX_RXDETECT_REF_LSB) #define GTYE3_CH_TXFIFO_ADDR_CFG_ADDR 0x007C #define GTYE3_CH_TXFIFO_ADDR_CFG_MSB 2 #define GTYE3_CH_TXFIFO_ADDR_CFG_LSB 2 #define GTYE3_CH_TXFIFO_ADDR_CFG_MASK BIT_MASK(GTYE3_CH_TXFIFO_ADDR_CFG_MSB, GTYE3_CH_TXFIFO_ADDR_CFG_LSB) #define GTYE3_CH_TXFIFO_ADDR_CFG_LOW 0 #define GTYE3_CH_TXFIFO_ADDR_CFG_HIGH 1 #define GTYE3_CH_TX_RXDETECT_CFG_ADDR 0x007D #define GTYE3_CH_TX_RXDETECT_CFG_MSB 15 #define GTYE3_CH_TX_RXDETECT_CFG_LSB 2 #define GTYE3_CH_TX_RXDETECT_CFG_MASK BIT_MASK(GTYE3_CH_TX_RXDETECT_CFG_MSB, GTYE3_CH_TX_RXDETECT_CFG_LSB) #define GTYE3_CH_TX_CLKMUX_EN_ADDR 0x007E #define GTYE3_CH_TX_CLKMUX_EN_MSB 15 #define GTYE3_CH_TX_CLKMUX_EN_LSB 15 #define GTYE3_CH_TX_CLKMUX_EN_MASK BIT_MASK(GTYE3_CH_TX_CLKMUX_EN_MSB, GTYE3_CH_TX_CLKMUX_EN_LSB) #define GTYE3_CH_TX_LOOPBACK_DRIVE_HIZ_ADDR 0x007E #define GTYE3_CH_TX_LOOPBACK_DRIVE_HIZ_MSB 14 #define GTYE3_CH_TX_LOOPBACK_DRIVE_HIZ_LSB 14 #define GTYE3_CH_TX_LOOPBACK_DRIVE_HIZ_MASK BIT_MASK(GTYE3_CH_TX_LOOPBACK_DRIVE_HIZ_MSB, GTYE3_CH_TX_LOOPBACK_DRIVE_HIZ_LSB) #define GTYE3_CH_TX_DRIVE_MODE_ADDR 0x007E #define GTYE3_CH_TX_DRIVE_MODE_MSB 12 #define GTYE3_CH_TX_DRIVE_MODE_LSB 8 #define GTYE3_CH_TX_DRIVE_MODE_MASK BIT_MASK(GTYE3_CH_TX_DRIVE_MODE_MSB, GTYE3_CH_TX_DRIVE_MODE_LSB) #define GTYE3_CH_TX_DRIVE_MODE_DIRECT 0 #define GTYE3_CH_TX_DRIVE_MODE_PIPE 1 #define GTYE3_CH_TX_DRIVE_MODE_PIPEGEN3 2 #define GTYE3_CH_TX_EIDLE_ASSERT_DELAY_ADDR 0x007E #define GTYE3_CH_TX_EIDLE_ASSERT_DELAY_MSB 7 #define GTYE3_CH_TX_EIDLE_ASSERT_DELAY_LSB 5 #define GTYE3_CH_TX_EIDLE_ASSERT_DELAY_MASK BIT_MASK(GTYE3_CH_TX_EIDLE_ASSERT_DELAY_MSB, GTYE3_CH_TX_EIDLE_ASSERT_DELAY_LSB) #define GTYE3_CH_TX_EIDLE_DEASSERT_DELAY_ADDR 0x007E #define GTYE3_CH_TX_EIDLE_DEASSERT_DELAY_MSB 4 #define GTYE3_CH_TX_EIDLE_DEASSERT_DELAY_LSB 2 #define GTYE3_CH_TX_EIDLE_DEASSERT_DELAY_MASK BIT_MASK(GTYE3_CH_TX_EIDLE_DEASSERT_DELAY_MSB, GTYE3_CH_TX_EIDLE_DEASSERT_DELAY_LSB) #define GTYE3_CH_TX_MARGIN_FULL_0_ADDR 0x007F #define GTYE3_CH_TX_MARGIN_FULL_0_MSB 15 #define GTYE3_CH_TX_MARGIN_FULL_0_LSB 9 #define GTYE3_CH_TX_MARGIN_FULL_0_MASK BIT_MASK(GTYE3_CH_TX_MARGIN_FULL_0_MSB, GTYE3_CH_TX_MARGIN_FULL_0_LSB) #define GTYE3_CH_TX_MARGIN_FULL_1_ADDR 0x007F #define GTYE3_CH_TX_MARGIN_FULL_1_MSB 7 #define GTYE3_CH_TX_MARGIN_FULL_1_LSB 1 #define GTYE3_CH_TX_MARGIN_FULL_1_MASK BIT_MASK(GTYE3_CH_TX_MARGIN_FULL_1_MSB, GTYE3_CH_TX_MARGIN_FULL_1_LSB) #define GTYE3_CH_TX_MARGIN_FULL_2_ADDR 0x0080 #define GTYE3_CH_TX_MARGIN_FULL_2_MSB 15 #define GTYE3_CH_TX_MARGIN_FULL_2_LSB 9 #define GTYE3_CH_TX_MARGIN_FULL_2_MASK BIT_MASK(GTYE3_CH_TX_MARGIN_FULL_2_MSB, GTYE3_CH_TX_MARGIN_FULL_2_LSB) #define GTYE3_CH_TX_MARGIN_FULL_3_ADDR 0x0080 #define GTYE3_CH_TX_MARGIN_FULL_3_MSB 7 #define GTYE3_CH_TX_MARGIN_FULL_3_LSB 1 #define GTYE3_CH_TX_MARGIN_FULL_3_MASK BIT_MASK(GTYE3_CH_TX_MARGIN_FULL_3_MSB, GTYE3_CH_TX_MARGIN_FULL_3_LSB) #define GTYE3_CH_TX_MARGIN_FULL_4_ADDR 0x0081 #define GTYE3_CH_TX_MARGIN_FULL_4_MSB 15 #define GTYE3_CH_TX_MARGIN_FULL_4_LSB 9 #define GTYE3_CH_TX_MARGIN_FULL_4_MASK BIT_MASK(GTYE3_CH_TX_MARGIN_FULL_4_MSB, GTYE3_CH_TX_MARGIN_FULL_4_LSB) #define GTYE3_CH_TX_MARGIN_LOW_0_ADDR 0x0081 #define GTYE3_CH_TX_MARGIN_LOW_0_MSB 7 #define GTYE3_CH_TX_MARGIN_LOW_0_LSB 1 #define GTYE3_CH_TX_MARGIN_LOW_0_MASK BIT_MASK(GTYE3_CH_TX_MARGIN_LOW_0_MSB, GTYE3_CH_TX_MARGIN_LOW_0_LSB) #define GTYE3_CH_TX_MARGIN_LOW_1_ADDR 0x0082 #define GTYE3_CH_TX_MARGIN_LOW_1_MSB 15 #define GTYE3_CH_TX_MARGIN_LOW_1_LSB 9 #define GTYE3_CH_TX_MARGIN_LOW_1_MASK BIT_MASK(GTYE3_CH_TX_MARGIN_LOW_1_MSB, GTYE3_CH_TX_MARGIN_LOW_1_LSB) #define GTYE3_CH_TX_MARGIN_LOW_2_ADDR 0x0082 #define GTYE3_CH_TX_MARGIN_LOW_2_MSB 7 #define GTYE3_CH_TX_MARGIN_LOW_2_LSB 1 #define GTYE3_CH_TX_MARGIN_LOW_2_MASK BIT_MASK(GTYE3_CH_TX_MARGIN_LOW_2_MSB, GTYE3_CH_TX_MARGIN_LOW_2_LSB) #define GTYE3_CH_TX_MARGIN_LOW_3_ADDR 0x0083 #define GTYE3_CH_TX_MARGIN_LOW_3_MSB 15 #define GTYE3_CH_TX_MARGIN_LOW_3_LSB 9 #define GTYE3_CH_TX_MARGIN_LOW_3_MASK BIT_MASK(GTYE3_CH_TX_MARGIN_LOW_3_MSB, GTYE3_CH_TX_MARGIN_LOW_3_LSB) #define GTYE3_CH_TX_MARGIN_LOW_4_ADDR 0x0083 #define GTYE3_CH_TX_MARGIN_LOW_4_MSB 7 #define GTYE3_CH_TX_MARGIN_LOW_4_LSB 1 #define GTYE3_CH_TX_MARGIN_LOW_4_MASK BIT_MASK(GTYE3_CH_TX_MARGIN_LOW_4_MSB, GTYE3_CH_TX_MARGIN_LOW_4_LSB) #define GTYE3_CH_RXDFE_HD_CFG1_ADDR 0x0084 #define GTYE3_CH_RXDFE_HD_CFG1_MSB 15 #define GTYE3_CH_RXDFE_HD_CFG1_LSB 0 #define GTYE3_CH_RXDFE_HD_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_HD_CFG1_MSB, GTYE3_CH_RXDFE_HD_CFG1_LSB) #define GTYE3_CH_TX_INT_DATAWIDTH_ADDR 0x0085 #define GTYE3_CH_TX_INT_DATAWIDTH_MSB 11 #define GTYE3_CH_TX_INT_DATAWIDTH_LSB 10 #define GTYE3_CH_TX_INT_DATAWIDTH_MASK BIT_MASK(GTYE3_CH_TX_INT_DATAWIDTH_MSB, GTYE3_CH_TX_INT_DATAWIDTH_LSB) #define GTYE3_CH_RXPRBS_LINKACQ_CNT_ADDR 0x0089 #define GTYE3_CH_RXPRBS_LINKACQ_CNT_MSB 7 #define GTYE3_CH_RXPRBS_LINKACQ_CNT_LSB 0 #define GTYE3_CH_RXPRBS_LINKACQ_CNT_MASK BIT_MASK(GTYE3_CH_RXPRBS_LINKACQ_CNT_MSB, GTYE3_CH_RXPRBS_LINKACQ_CNT_LSB) #define GTYE3_CH_TX_PMADATA_OPT_ADDR 0x008A #define GTYE3_CH_TX_PMADATA_OPT_MSB 15 #define GTYE3_CH_TX_PMADATA_OPT_LSB 15 #define GTYE3_CH_TX_PMADATA_OPT_MASK BIT_MASK(GTYE3_CH_TX_PMADATA_OPT_MSB, GTYE3_CH_TX_PMADATA_OPT_LSB) #define GTYE3_CH_RXSYNC_OVRD_ADDR 0x008A #define GTYE3_CH_RXSYNC_OVRD_MSB 14 #define GTYE3_CH_RXSYNC_OVRD_LSB 14 #define GTYE3_CH_RXSYNC_OVRD_MASK BIT_MASK(GTYE3_CH_RXSYNC_OVRD_MSB, GTYE3_CH_RXSYNC_OVRD_LSB) #define GTYE3_CH_TXSYNC_OVRD_ADDR 0x008A #define GTYE3_CH_TXSYNC_OVRD_MSB 13 #define GTYE3_CH_TXSYNC_OVRD_LSB 13 #define GTYE3_CH_TXSYNC_OVRD_MASK BIT_MASK(GTYE3_CH_TXSYNC_OVRD_MSB, GTYE3_CH_TXSYNC_OVRD_LSB) #define GTYE3_CH_TX_IDLE_DATA_ZERO_ADDR 0x008A #define GTYE3_CH_TX_IDLE_DATA_ZERO_MSB 12 #define GTYE3_CH_TX_IDLE_DATA_ZERO_LSB 12 #define GTYE3_CH_TX_IDLE_DATA_ZERO_MASK BIT_MASK(GTYE3_CH_TX_IDLE_DATA_ZERO_MSB, GTYE3_CH_TX_IDLE_DATA_ZERO_LSB) #define GTYE3_CH_A_RXOSCALRESET_ADDR 0x008A #define GTYE3_CH_A_RXOSCALRESET_MSB 11 #define GTYE3_CH_A_RXOSCALRESET_LSB 11 #define GTYE3_CH_A_RXOSCALRESET_MASK BIT_MASK(GTYE3_CH_A_RXOSCALRESET_MSB, GTYE3_CH_A_RXOSCALRESET_LSB) #define GTYE3_CH_RXOOB_CLK_CFG_ADDR 0x008A #define GTYE3_CH_RXOOB_CLK_CFG_MSB 10 #define GTYE3_CH_RXOOB_CLK_CFG_LSB 10 #define GTYE3_CH_RXOOB_CLK_CFG_MASK BIT_MASK(GTYE3_CH_RXOOB_CLK_CFG_MSB, GTYE3_CH_RXOOB_CLK_CFG_LSB) #define GTYE3_CH_RXOOB_CLK_CFG_PMA 0 #define GTYE3_CH_RXOOB_CLK_CFG_FABRIC 1 #define GTYE3_CH_TXSYNC_SKIP_DA_ADDR 0x008A #define GTYE3_CH_TXSYNC_SKIP_DA_MSB 9 #define GTYE3_CH_TXSYNC_SKIP_DA_LSB 9 #define GTYE3_CH_TXSYNC_SKIP_DA_MASK BIT_MASK(GTYE3_CH_TXSYNC_SKIP_DA_MSB, GTYE3_CH_TXSYNC_SKIP_DA_LSB) #define GTYE3_CH_RXSYNC_SKIP_DA_ADDR 0x008A #define GTYE3_CH_RXSYNC_SKIP_DA_MSB 8 #define GTYE3_CH_RXSYNC_SKIP_DA_LSB 8 #define GTYE3_CH_RXSYNC_SKIP_DA_MASK BIT_MASK(GTYE3_CH_RXSYNC_SKIP_DA_MSB, GTYE3_CH_RXSYNC_SKIP_DA_LSB) #define GTYE3_CH_RXCFOKDONE_SRC_ADDR 0x008A #define GTYE3_CH_RXCFOKDONE_SRC_MSB 6 #define GTYE3_CH_RXCFOKDONE_SRC_LSB 5 #define GTYE3_CH_RXCFOKDONE_SRC_MASK BIT_MASK(GTYE3_CH_RXCFOKDONE_SRC_MSB, GTYE3_CH_RXCFOKDONE_SRC_LSB) #define GTYE3_CH_RXOSCALRESET_TIME_ADDR 0x008A #define GTYE3_CH_RXOSCALRESET_TIME_MSB 4 #define GTYE3_CH_RXOSCALRESET_TIME_LSB 0 #define GTYE3_CH_RXOSCALRESET_TIME_MASK BIT_MASK(GTYE3_CH_RXOSCALRESET_TIME_MSB, GTYE3_CH_RXOSCALRESET_TIME_LSB) #define GTYE3_CH_TXSYNC_MULTILANE_ADDR 0x008B #define GTYE3_CH_TXSYNC_MULTILANE_MSB 10 #define GTYE3_CH_TXSYNC_MULTILANE_LSB 10 #define GTYE3_CH_TXSYNC_MULTILANE_MASK BIT_MASK(GTYE3_CH_TXSYNC_MULTILANE_MSB, GTYE3_CH_TXSYNC_MULTILANE_LSB) #define GTYE3_CH_RXSYNC_MULTILANE_ADDR 0x008B #define GTYE3_CH_RXSYNC_MULTILANE_MSB 9 #define GTYE3_CH_RXSYNC_MULTILANE_LSB 9 #define GTYE3_CH_RXSYNC_MULTILANE_MASK BIT_MASK(GTYE3_CH_RXSYNC_MULTILANE_MSB, GTYE3_CH_RXSYNC_MULTILANE_LSB) #define GTYE3_CH_ACJTAG_MODE_ADDR 0x008C #define GTYE3_CH_ACJTAG_MODE_MSB 15 #define GTYE3_CH_ACJTAG_MODE_LSB 15 #define GTYE3_CH_ACJTAG_MODE_MASK BIT_MASK(GTYE3_CH_ACJTAG_MODE_MSB, GTYE3_CH_ACJTAG_MODE_LSB) #define GTYE3_CH_ACJTAG_DEBUG_MODE_ADDR 0x008C #define GTYE3_CH_ACJTAG_DEBUG_MODE_MSB 14 #define GTYE3_CH_ACJTAG_DEBUG_MODE_LSB 14 #define GTYE3_CH_ACJTAG_DEBUG_MODE_MASK BIT_MASK(GTYE3_CH_ACJTAG_DEBUG_MODE_MSB, GTYE3_CH_ACJTAG_DEBUG_MODE_LSB) #define GTYE3_CH_ACJTAG_RESET_ADDR 0x008C #define GTYE3_CH_ACJTAG_RESET_MSB 13 #define GTYE3_CH_ACJTAG_RESET_LSB 13 #define GTYE3_CH_ACJTAG_RESET_MASK BIT_MASK(GTYE3_CH_ACJTAG_RESET_MSB, GTYE3_CH_ACJTAG_RESET_LSB) #define GTYE3_CH_RESET_POWERSAVE_DISABLE_ADDR 0x008C #define GTYE3_CH_RESET_POWERSAVE_DISABLE_MSB 12 #define GTYE3_CH_RESET_POWERSAVE_DISABLE_LSB 12 #define GTYE3_CH_RESET_POWERSAVE_DISABLE_MASK BIT_MASK(GTYE3_CH_RESET_POWERSAVE_DISABLE_MSB, GTYE3_CH_RESET_POWERSAVE_DISABLE_LSB) #define GTYE3_CH_RX_TUNE_AFE_OS_ADDR 0x008C #define GTYE3_CH_RX_TUNE_AFE_OS_MSB 11 #define GTYE3_CH_RX_TUNE_AFE_OS_LSB 10 #define GTYE3_CH_RX_TUNE_AFE_OS_MASK BIT_MASK(GTYE3_CH_RX_TUNE_AFE_OS_MSB, GTYE3_CH_RX_TUNE_AFE_OS_LSB) #define GTYE3_CH_RX_DFE_KL_LPM_KL_CFG0_ADDR 0x008C #define GTYE3_CH_RX_DFE_KL_LPM_KL_CFG0_MSB 9 #define GTYE3_CH_RX_DFE_KL_LPM_KL_CFG0_LSB 8 #define GTYE3_CH_RX_DFE_KL_LPM_KL_CFG0_MASK BIT_MASK(GTYE3_CH_RX_DFE_KL_LPM_KL_CFG0_MSB, GTYE3_CH_RX_DFE_KL_LPM_KL_CFG0_LSB) #define GTYE3_CH_RX_DFE_KL_LPM_KL_CFG1_ADDR 0x008C #define GTYE3_CH_RX_DFE_KL_LPM_KL_CFG1_MSB 7 #define GTYE3_CH_RX_DFE_KL_LPM_KL_CFG1_LSB 5 #define GTYE3_CH_RX_DFE_KL_LPM_KL_CFG1_MASK BIT_MASK(GTYE3_CH_RX_DFE_KL_LPM_KL_CFG1_MSB, GTYE3_CH_RX_DFE_KL_LPM_KL_CFG1_LSB) #define GTYE3_CH_RXDFELPM_KL_CFG2_ADDR 0x008D #define GTYE3_CH_RXDFELPM_KL_CFG2_MSB 15 #define GTYE3_CH_RXDFELPM_KL_CFG2_LSB 0 #define GTYE3_CH_RXDFELPM_KL_CFG2_MASK BIT_MASK(GTYE3_CH_RXDFELPM_KL_CFG2_MSB, GTYE3_CH_RXDFELPM_KL_CFG2_LSB) #define GTYE3_CH_RXDFE_VP_CFG0_ADDR 0x008E #define GTYE3_CH_RXDFE_VP_CFG0_MSB 15 #define GTYE3_CH_RXDFE_VP_CFG0_LSB 0 #define GTYE3_CH_RXDFE_VP_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_VP_CFG0_MSB, GTYE3_CH_RXDFE_VP_CFG0_LSB) #define GTYE3_CH_RXDFE_VP_CFG1_ADDR 0x008F #define GTYE3_CH_RXDFE_VP_CFG1_MSB 15 #define GTYE3_CH_RXDFE_VP_CFG1_LSB 0 #define GTYE3_CH_RXDFE_VP_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_VP_CFG1_MSB, GTYE3_CH_RXDFE_VP_CFG1_LSB) #define GTYE3_CH_RXDFE_UT_CFG1_ADDR 0x0090 #define GTYE3_CH_RXDFE_UT_CFG1_MSB 15 #define GTYE3_CH_RXDFE_UT_CFG1_LSB 0 #define GTYE3_CH_RXDFE_UT_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_UT_CFG1_MSB, GTYE3_CH_RXDFE_UT_CFG1_LSB) #define GTYE3_CH_ADAPT_CFG0_ADDR 0x0091 #define GTYE3_CH_ADAPT_CFG0_MSB 15 #define GTYE3_CH_ADAPT_CFG0_LSB 0 #define GTYE3_CH_ADAPT_CFG0_MASK BIT_MASK(GTYE3_CH_ADAPT_CFG0_MSB, GTYE3_CH_ADAPT_CFG0_LSB) #define GTYE3_CH_ADAPT_CFG1_ADDR 0x0092 #define GTYE3_CH_ADAPT_CFG1_MSB 15 #define GTYE3_CH_ADAPT_CFG1_LSB 0 #define GTYE3_CH_ADAPT_CFG1_MASK BIT_MASK(GTYE3_CH_ADAPT_CFG1_MSB, GTYE3_CH_ADAPT_CFG1_LSB) #define GTYE3_CH_RXCFOK_CFG0_ADDR 0x0093 #define GTYE3_CH_RXCFOK_CFG0_MSB 15 #define GTYE3_CH_RXCFOK_CFG0_LSB 0 #define GTYE3_CH_RXCFOK_CFG0_MASK BIT_MASK(GTYE3_CH_RXCFOK_CFG0_MSB, GTYE3_CH_RXCFOK_CFG0_LSB) #define GTYE3_CH_ES_CLK_PHASE_SEL_ADDR 0x0094 #define GTYE3_CH_ES_CLK_PHASE_SEL_MSB 11 #define GTYE3_CH_ES_CLK_PHASE_SEL_LSB 11 #define GTYE3_CH_ES_CLK_PHASE_SEL_MASK BIT_MASK(GTYE3_CH_ES_CLK_PHASE_SEL_MSB, GTYE3_CH_ES_CLK_PHASE_SEL_LSB) #define GTYE3_CH_USE_PCS_CLK_PHASE_SEL_ADDR 0x0094 #define GTYE3_CH_USE_PCS_CLK_PHASE_SEL_MSB 10 #define GTYE3_CH_USE_PCS_CLK_PHASE_SEL_LSB 10 #define GTYE3_CH_USE_PCS_CLK_PHASE_SEL_MASK BIT_MASK(GTYE3_CH_USE_PCS_CLK_PHASE_SEL_MSB, GTYE3_CH_USE_PCS_CLK_PHASE_SEL_LSB) #define GTYE3_CH_PMA_RSV1_ADDR 0x0095 #define GTYE3_CH_PMA_RSV1_MSB 15 #define GTYE3_CH_PMA_RSV1_LSB 0 #define GTYE3_CH_PMA_RSV1_MASK BIT_MASK(GTYE3_CH_PMA_RSV1_MSB, GTYE3_CH_PMA_RSV1_LSB) #define GTYE3_CH_RX_AFE_CM_EN_ADDR 0x0097 #define GTYE3_CH_RX_AFE_CM_EN_MSB 12 #define GTYE3_CH_RX_AFE_CM_EN_LSB 12 #define GTYE3_CH_RX_AFE_CM_EN_MASK BIT_MASK(GTYE3_CH_RX_AFE_CM_EN_MSB, GTYE3_CH_RX_AFE_CM_EN_LSB) #define GTYE3_CH_RX_CAPFF_SARC_ENB_ADDR 0x0097 #define GTYE3_CH_RX_CAPFF_SARC_ENB_MSB 11 #define GTYE3_CH_RX_CAPFF_SARC_ENB_LSB 11 #define GTYE3_CH_RX_CAPFF_SARC_ENB_MASK BIT_MASK(GTYE3_CH_RX_CAPFF_SARC_ENB_MSB, GTYE3_CH_RX_CAPFF_SARC_ENB_LSB) #define GTYE3_CH_RX_EYESCAN_VS_NEG_DIR_ADDR 0x0097 #define GTYE3_CH_RX_EYESCAN_VS_NEG_DIR_MSB 10 #define GTYE3_CH_RX_EYESCAN_VS_NEG_DIR_LSB 10 #define GTYE3_CH_RX_EYESCAN_VS_NEG_DIR_MASK BIT_MASK(GTYE3_CH_RX_EYESCAN_VS_NEG_DIR_MSB, GTYE3_CH_RX_EYESCAN_VS_NEG_DIR_LSB) #define GTYE3_CH_RX_EYESCAN_VS_UT_SIGN_ADDR 0x0097 #define GTYE3_CH_RX_EYESCAN_VS_UT_SIGN_MSB 9 #define GTYE3_CH_RX_EYESCAN_VS_UT_SIGN_LSB 9 #define GTYE3_CH_RX_EYESCAN_VS_UT_SIGN_MASK BIT_MASK(GTYE3_CH_RX_EYESCAN_VS_UT_SIGN_MSB, GTYE3_CH_RX_EYESCAN_VS_UT_SIGN_LSB) #define GTYE3_CH_RX_EYESCAN_VS_CODE_ADDR 0x0097 #define GTYE3_CH_RX_EYESCAN_VS_CODE_MSB 8 #define GTYE3_CH_RX_EYESCAN_VS_CODE_LSB 2 #define GTYE3_CH_RX_EYESCAN_VS_CODE_MASK BIT_MASK(GTYE3_CH_RX_EYESCAN_VS_CODE_MSB, GTYE3_CH_RX_EYESCAN_VS_CODE_LSB) #define GTYE3_CH_RX_EYESCAN_VS_RANGE_ADDR 0x0097 #define GTYE3_CH_RX_EYESCAN_VS_RANGE_MSB 1 #define GTYE3_CH_RX_EYESCAN_VS_RANGE_LSB 0 #define GTYE3_CH_RX_EYESCAN_VS_RANGE_MASK BIT_MASK(GTYE3_CH_RX_EYESCAN_VS_RANGE_MSB, GTYE3_CH_RX_EYESCAN_VS_RANGE_LSB) #define GTYE3_CH_RXDFE_HE_CFG1_ADDR 0x0098 #define GTYE3_CH_RXDFE_HE_CFG1_MSB 15 #define GTYE3_CH_RXDFE_HE_CFG1_LSB 0 #define GTYE3_CH_RXDFE_HE_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_HE_CFG1_MSB, GTYE3_CH_RXDFE_HE_CFG1_LSB) #define GTYE3_CH_GEARBOX_MODE_ADDR 0x0099 #define GTYE3_CH_GEARBOX_MODE_MSB 15 #define GTYE3_CH_GEARBOX_MODE_LSB 11 #define GTYE3_CH_GEARBOX_MODE_MASK BIT_MASK(GTYE3_CH_GEARBOX_MODE_MSB, GTYE3_CH_GEARBOX_MODE_LSB) #define GTYE3_CH_TXPI_SYNFREQ_PPM_ADDR 0x0099 #define GTYE3_CH_TXPI_SYNFREQ_PPM_MSB 10 #define GTYE3_CH_TXPI_SYNFREQ_PPM_LSB 8 #define GTYE3_CH_TXPI_SYNFREQ_PPM_MASK BIT_MASK(GTYE3_CH_TXPI_SYNFREQ_PPM_MSB, GTYE3_CH_TXPI_SYNFREQ_PPM_LSB) #define GTYE3_CH_TXPI_PPMCLK_SEL_ADDR 0x0099 #define GTYE3_CH_TXPI_PPMCLK_SEL_MSB 7 #define GTYE3_CH_TXPI_PPMCLK_SEL_LSB 7 #define GTYE3_CH_TXPI_PPMCLK_SEL_MASK BIT_MASK(GTYE3_CH_TXPI_PPMCLK_SEL_MSB, GTYE3_CH_TXPI_PPMCLK_SEL_LSB) #define GTYE3_CH_TXPI_PPMCLK_SEL_TXUSRCLK 0 #define GTYE3_CH_TXPI_PPMCLK_SEL_TXUSRCLK2 1 #define GTYE3_CH_TXPI_INVSTROBE_SEL_ADDR 0x0099 #define GTYE3_CH_TXPI_INVSTROBE_SEL_MSB 6 #define GTYE3_CH_TXPI_INVSTROBE_SEL_LSB 6 #define GTYE3_CH_TXPI_INVSTROBE_SEL_MASK BIT_MASK(GTYE3_CH_TXPI_INVSTROBE_SEL_MSB, GTYE3_CH_TXPI_INVSTROBE_SEL_LSB) #define GTYE3_CH_TXPI_GRAY_SEL_ADDR 0x0099 #define GTYE3_CH_TXPI_GRAY_SEL_MSB 5 #define GTYE3_CH_TXPI_GRAY_SEL_LSB 5 #define GTYE3_CH_TXPI_GRAY_SEL_MASK BIT_MASK(GTYE3_CH_TXPI_GRAY_SEL_MSB, GTYE3_CH_TXPI_GRAY_SEL_LSB) #define GTYE3_CH_TXPI_LPM_ADDR 0x0099 #define GTYE3_CH_TXPI_LPM_MSB 3 #define GTYE3_CH_TXPI_LPM_LSB 3 #define GTYE3_CH_TXPI_LPM_MASK BIT_MASK(GTYE3_CH_TXPI_LPM_MSB, GTYE3_CH_TXPI_LPM_LSB) #define GTYE3_CH_TXPI_VREFSEL_ADDR 0x0099 #define GTYE3_CH_TXPI_VREFSEL_MSB 2 #define GTYE3_CH_TXPI_VREFSEL_LSB 2 #define GTYE3_CH_TXPI_VREFSEL_MASK BIT_MASK(GTYE3_CH_TXPI_VREFSEL_MSB, GTYE3_CH_TXPI_VREFSEL_LSB) #define GTYE3_CH_TXPI_PPM_CFG_ADDR 0x009A #define GTYE3_CH_TXPI_PPM_CFG_MSB 7 #define GTYE3_CH_TXPI_PPM_CFG_LSB 0 #define GTYE3_CH_TXPI_PPM_CFG_MASK BIT_MASK(GTYE3_CH_TXPI_PPM_CFG_MSB, GTYE3_CH_TXPI_PPM_CFG_LSB) #define GTYE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_ADDR 0x009B #define GTYE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_MSB 15 #define GTYE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_LSB 15 #define GTYE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_MASK BIT_MASK(GTYE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_MSB, GTYE3_CH_RX_DFELPM_KLKH_AGC_STUP_EN_LSB) #define GTYE3_CH_RX_DFELPM_CFG0_ADDR 0x009B #define GTYE3_CH_RX_DFELPM_CFG0_MSB 14 #define GTYE3_CH_RX_DFELPM_CFG0_LSB 11 #define GTYE3_CH_RX_DFELPM_CFG0_MASK BIT_MASK(GTYE3_CH_RX_DFELPM_CFG0_MSB, GTYE3_CH_RX_DFELPM_CFG0_LSB) #define GTYE3_CH_RX_DFELPM_CFG1_ADDR 0x009B #define GTYE3_CH_RX_DFELPM_CFG1_MSB 10 #define GTYE3_CH_RX_DFELPM_CFG1_LSB 10 #define GTYE3_CH_RX_DFELPM_CFG1_MASK BIT_MASK(GTYE3_CH_RX_DFELPM_CFG1_MSB, GTYE3_CH_RX_DFELPM_CFG1_LSB) #define GTYE3_CH_RX_DFE_KL_LPM_KH_CFG0_ADDR 0x009B #define GTYE3_CH_RX_DFE_KL_LPM_KH_CFG0_MSB 9 #define GTYE3_CH_RX_DFE_KL_LPM_KH_CFG0_LSB 8 #define GTYE3_CH_RX_DFE_KL_LPM_KH_CFG0_MASK BIT_MASK(GTYE3_CH_RX_DFE_KL_LPM_KH_CFG0_MSB, GTYE3_CH_RX_DFE_KL_LPM_KH_CFG0_LSB) #define GTYE3_CH_RX_DFE_KL_LPM_KH_CFG1_ADDR 0x009B #define GTYE3_CH_RX_DFE_KL_LPM_KH_CFG1_MSB 7 #define GTYE3_CH_RX_DFE_KL_LPM_KH_CFG1_LSB 5 #define GTYE3_CH_RX_DFE_KL_LPM_KH_CFG1_MASK BIT_MASK(GTYE3_CH_RX_DFE_KL_LPM_KH_CFG1_MSB, GTYE3_CH_RX_DFE_KL_LPM_KH_CFG1_LSB) #define GTYE3_CH_TXPI_CFG0_ADDR 0x009C #define GTYE3_CH_TXPI_CFG0_MSB 12 #define GTYE3_CH_TXPI_CFG0_LSB 11 #define GTYE3_CH_TXPI_CFG0_MASK BIT_MASK(GTYE3_CH_TXPI_CFG0_MSB, GTYE3_CH_TXPI_CFG0_LSB) #define GTYE3_CH_TXPI_CFG1_ADDR 0x009C #define GTYE3_CH_TXPI_CFG1_MSB 10 #define GTYE3_CH_TXPI_CFG1_LSB 9 #define GTYE3_CH_TXPI_CFG1_MASK BIT_MASK(GTYE3_CH_TXPI_CFG1_MSB, GTYE3_CH_TXPI_CFG1_LSB) #define GTYE3_CH_TXPI_CFG2_ADDR 0x009C #define GTYE3_CH_TXPI_CFG2_MSB 8 #define GTYE3_CH_TXPI_CFG2_LSB 7 #define GTYE3_CH_TXPI_CFG2_MASK BIT_MASK(GTYE3_CH_TXPI_CFG2_MSB, GTYE3_CH_TXPI_CFG2_LSB) #define GTYE3_CH_TXPI_CFG3_ADDR 0x009C #define GTYE3_CH_TXPI_CFG3_MSB 6 #define GTYE3_CH_TXPI_CFG3_LSB 6 #define GTYE3_CH_TXPI_CFG3_MASK BIT_MASK(GTYE3_CH_TXPI_CFG3_MSB, GTYE3_CH_TXPI_CFG3_LSB) #define GTYE3_CH_TXPI_CFG4_ADDR 0x009C #define GTYE3_CH_TXPI_CFG4_MSB 5 #define GTYE3_CH_TXPI_CFG4_LSB 5 #define GTYE3_CH_TXPI_CFG4_MASK BIT_MASK(GTYE3_CH_TXPI_CFG4_MSB, GTYE3_CH_TXPI_CFG4_LSB) #define GTYE3_CH_TXPI_CFG5_ADDR 0x009C #define GTYE3_CH_TXPI_CFG5_MSB 4 #define GTYE3_CH_TXPI_CFG5_LSB 2 #define GTYE3_CH_TXPI_CFG5_MASK BIT_MASK(GTYE3_CH_TXPI_CFG5_MSB, GTYE3_CH_TXPI_CFG5_LSB) #define GTYE3_CH_RXPI_CFG_ADDR 0x009D #define GTYE3_CH_RXPI_CFG_MSB 15 #define GTYE3_CH_RXPI_CFG_LSB 0 #define GTYE3_CH_RXPI_CFG_MASK BIT_MASK(GTYE3_CH_RXPI_CFG_MSB, GTYE3_CH_RXPI_CFG_LSB) #define GTYE3_CH_RXDFE_UT_CFG0_ADDR 0x009E #define GTYE3_CH_RXDFE_UT_CFG0_MSB 15 #define GTYE3_CH_RXDFE_UT_CFG0_LSB 0 #define GTYE3_CH_RXDFE_UT_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_UT_CFG0_MSB, GTYE3_CH_RXDFE_UT_CFG0_LSB) #define GTYE3_CH_RXDFE_GC_CFG0_ADDR 0x009F #define GTYE3_CH_RXDFE_GC_CFG0_MSB 15 #define GTYE3_CH_RXDFE_GC_CFG0_LSB 0 #define GTYE3_CH_RXDFE_GC_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_GC_CFG0_MSB, GTYE3_CH_RXDFE_GC_CFG0_LSB) #define GTYE3_CH_RXDFE_GC_CFG1_ADDR 0x00A0 #define GTYE3_CH_RXDFE_GC_CFG1_MSB 15 #define GTYE3_CH_RXDFE_GC_CFG1_LSB 0 #define GTYE3_CH_RXDFE_GC_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_GC_CFG1_MSB, GTYE3_CH_RXDFE_GC_CFG1_LSB) #define GTYE3_CH_RXDFE_GC_CFG2_ADDR 0x00A1 #define GTYE3_CH_RXDFE_GC_CFG2_MSB 15 #define GTYE3_CH_RXDFE_GC_CFG2_LSB 0 #define GTYE3_CH_RXDFE_GC_CFG2_MASK BIT_MASK(GTYE3_CH_RXDFE_GC_CFG2_MSB, GTYE3_CH_RXDFE_GC_CFG2_LSB) #define GTYE3_CH_RXCDR_CFG0_GEN3_ADDR 0x00A2 #define GTYE3_CH_RXCDR_CFG0_GEN3_MSB 15 #define GTYE3_CH_RXCDR_CFG0_GEN3_LSB 0 #define GTYE3_CH_RXCDR_CFG0_GEN3_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG0_GEN3_MSB, GTYE3_CH_RXCDR_CFG0_GEN3_LSB) #define GTYE3_CH_RXCDR_CFG1_GEN3_ADDR 0x00A3 #define GTYE3_CH_RXCDR_CFG1_GEN3_MSB 15 #define GTYE3_CH_RXCDR_CFG1_GEN3_LSB 0 #define GTYE3_CH_RXCDR_CFG1_GEN3_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG1_GEN3_MSB, GTYE3_CH_RXCDR_CFG1_GEN3_LSB) #define GTYE3_CH_RXCDR_CFG2_GEN3_ADDR 0x00A4 #define GTYE3_CH_RXCDR_CFG2_GEN3_MSB 15 #define GTYE3_CH_RXCDR_CFG2_GEN3_LSB 0 #define GTYE3_CH_RXCDR_CFG2_GEN3_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG2_GEN3_MSB, GTYE3_CH_RXCDR_CFG2_GEN3_LSB) #define GTYE3_CH_RXCDR_CFG3_GEN3_ADDR 0x00A5 #define GTYE3_CH_RXCDR_CFG3_GEN3_MSB 15 #define GTYE3_CH_RXCDR_CFG3_GEN3_LSB 0 #define GTYE3_CH_RXCDR_CFG3_GEN3_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG3_GEN3_MSB, GTYE3_CH_RXCDR_CFG3_GEN3_LSB) #define GTYE3_CH_RXCDR_CFG4_GEN3_ADDR 0x00A6 #define GTYE3_CH_RXCDR_CFG4_GEN3_MSB 15 #define GTYE3_CH_RXCDR_CFG4_GEN3_LSB 0 #define GTYE3_CH_RXCDR_CFG4_GEN3_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG4_GEN3_MSB, GTYE3_CH_RXCDR_CFG4_GEN3_LSB) #define GTYE3_CH_RXCDR_CFG5_GEN3_ADDR 0x00A7 #define GTYE3_CH_RXCDR_CFG5_GEN3_MSB 15 #define GTYE3_CH_RXCDR_CFG5_GEN3_LSB 0 #define GTYE3_CH_RXCDR_CFG5_GEN3_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG5_GEN3_MSB, GTYE3_CH_RXCDR_CFG5_GEN3_LSB) #define GTYE3_CH_RXCDR_CFG5_ADDR 0x00A8 #define GTYE3_CH_RXCDR_CFG5_MSB 15 #define GTYE3_CH_RXCDR_CFG5_LSB 0 #define GTYE3_CH_RXCDR_CFG5_MASK BIT_MASK(GTYE3_CH_RXCDR_CFG5_MSB, GTYE3_CH_RXCDR_CFG5_LSB) #define GTYE3_CH_PCIE_RXPMA_CFG_ADDR 0x00A9 #define GTYE3_CH_PCIE_RXPMA_CFG_MSB 15 #define GTYE3_CH_PCIE_RXPMA_CFG_LSB 0 #define GTYE3_CH_PCIE_RXPMA_CFG_MASK BIT_MASK(GTYE3_CH_PCIE_RXPMA_CFG_MSB, GTYE3_CH_PCIE_RXPMA_CFG_LSB) #define GTYE3_CH_PCIE_TXPCS_CFG_GEN3_ADDR 0x00AA #define GTYE3_CH_PCIE_TXPCS_CFG_GEN3_MSB 15 #define GTYE3_CH_PCIE_TXPCS_CFG_GEN3_LSB 0 #define GTYE3_CH_PCIE_TXPCS_CFG_GEN3_MASK BIT_MASK(GTYE3_CH_PCIE_TXPCS_CFG_GEN3_MSB, GTYE3_CH_PCIE_TXPCS_CFG_GEN3_LSB) #define GTYE3_CH_PCIE_TXPMA_CFG_ADDR 0x00AB #define GTYE3_CH_PCIE_TXPMA_CFG_MSB 15 #define GTYE3_CH_PCIE_TXPMA_CFG_LSB 0 #define GTYE3_CH_PCIE_TXPMA_CFG_MASK BIT_MASK(GTYE3_CH_PCIE_TXPMA_CFG_MSB, GTYE3_CH_PCIE_TXPMA_CFG_LSB) #define GTYE3_CH_RX_CLK_SLIP_OVRD_ADDR 0x00AC #define GTYE3_CH_RX_CLK_SLIP_OVRD_MSB 7 #define GTYE3_CH_RX_CLK_SLIP_OVRD_LSB 3 #define GTYE3_CH_RX_CLK_SLIP_OVRD_MASK BIT_MASK(GTYE3_CH_RX_CLK_SLIP_OVRD_MSB, GTYE3_CH_RX_CLK_SLIP_OVRD_LSB) #define GTYE3_CH_PCS_RSVD1_ADDR 0x00AC #define GTYE3_CH_PCS_RSVD1_MSB 2 #define GTYE3_CH_PCS_RSVD1_LSB 0 #define GTYE3_CH_PCS_RSVD1_MASK BIT_MASK(GTYE3_CH_PCS_RSVD1_MSB, GTYE3_CH_PCS_RSVD1_LSB) #define GTYE3_CH_PLL_SEL_MODE_GEN3_ADDR 0x00AD #define GTYE3_CH_PLL_SEL_MODE_GEN3_MSB 12 #define GTYE3_CH_PLL_SEL_MODE_GEN3_LSB 11 #define GTYE3_CH_PLL_SEL_MODE_GEN3_MASK BIT_MASK(GTYE3_CH_PLL_SEL_MODE_GEN3_MSB, GTYE3_CH_PLL_SEL_MODE_GEN3_LSB) #define GTYE3_CH_PLL_SEL_MODE_GEN12_ADDR 0x00AD #define GTYE3_CH_PLL_SEL_MODE_GEN12_MSB 10 #define GTYE3_CH_PLL_SEL_MODE_GEN12_LSB 9 #define GTYE3_CH_PLL_SEL_MODE_GEN12_MASK BIT_MASK(GTYE3_CH_PLL_SEL_MODE_GEN12_MSB, GTYE3_CH_PLL_SEL_MODE_GEN12_LSB) #define GTYE3_CH_RATE_SW_USE_DRP_ADDR 0x00AD #define GTYE3_CH_RATE_SW_USE_DRP_MSB 8 #define GTYE3_CH_RATE_SW_USE_DRP_LSB 8 #define GTYE3_CH_RATE_SW_USE_DRP_MASK BIT_MASK(GTYE3_CH_RATE_SW_USE_DRP_MSB, GTYE3_CH_RATE_SW_USE_DRP_LSB) #define GTYE3_CH_RXPI_LPM_ADDR 0x00AD #define GTYE3_CH_RXPI_LPM_MSB 3 #define GTYE3_CH_RXPI_LPM_LSB 3 #define GTYE3_CH_RXPI_LPM_MASK BIT_MASK(GTYE3_CH_RXPI_LPM_MSB, GTYE3_CH_RXPI_LPM_LSB) #define GTYE3_CH_RXPI_VREFSEL_ADDR 0x00AD #define GTYE3_CH_RXPI_VREFSEL_MSB 2 #define GTYE3_CH_RXPI_VREFSEL_LSB 2 #define GTYE3_CH_RXPI_VREFSEL_MASK BIT_MASK(GTYE3_CH_RXPI_VREFSEL_MSB, GTYE3_CH_RXPI_VREFSEL_LSB) #define GTYE3_CH_RXPI_SEL_LC_ADDR 0x00AD #define GTYE3_CH_RXPI_SEL_LC_MSB 1 #define GTYE3_CH_RXPI_SEL_LC_LSB 0 #define GTYE3_CH_RXPI_SEL_LC_MASK BIT_MASK(GTYE3_CH_RXPI_SEL_LC_MSB, GTYE3_CH_RXPI_SEL_LC_LSB) #define GTYE3_CH_RXDFE_H3_CFG0_ADDR 0x00AE #define GTYE3_CH_RXDFE_H3_CFG0_MSB 15 #define GTYE3_CH_RXDFE_H3_CFG0_LSB 0 #define GTYE3_CH_RXDFE_H3_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_H3_CFG0_MSB, GTYE3_CH_RXDFE_H3_CFG0_LSB) #define GTYE3_CH_DFE_D_X_REL_POS_ADDR 0x00AF #define GTYE3_CH_DFE_D_X_REL_POS_MSB 15 #define GTYE3_CH_DFE_D_X_REL_POS_LSB 15 #define GTYE3_CH_DFE_D_X_REL_POS_MASK BIT_MASK(GTYE3_CH_DFE_D_X_REL_POS_MSB, GTYE3_CH_DFE_D_X_REL_POS_LSB) #define GTYE3_CH_DFE_VCM_COMP_EN_ADDR 0x00AF #define GTYE3_CH_DFE_VCM_COMP_EN_MSB 14 #define GTYE3_CH_DFE_VCM_COMP_EN_LSB 14 #define GTYE3_CH_DFE_VCM_COMP_EN_MASK BIT_MASK(GTYE3_CH_DFE_VCM_COMP_EN_MSB, GTYE3_CH_DFE_VCM_COMP_EN_LSB) #define GTYE3_CH_GM_BIAS_SELECT_ADDR 0x00AF #define GTYE3_CH_GM_BIAS_SELECT_MSB 13 #define GTYE3_CH_GM_BIAS_SELECT_LSB 13 #define GTYE3_CH_GM_BIAS_SELECT_MASK BIT_MASK(GTYE3_CH_GM_BIAS_SELECT_MSB, GTYE3_CH_GM_BIAS_SELECT_LSB) #define GTYE3_CH_EVODD_PHI_CFG_ADDR 0x00AF #define GTYE3_CH_EVODD_PHI_CFG_MSB 10 #define GTYE3_CH_EVODD_PHI_CFG_LSB 0 #define GTYE3_CH_EVODD_PHI_CFG_MASK BIT_MASK(GTYE3_CH_EVODD_PHI_CFG_MSB, GTYE3_CH_EVODD_PHI_CFG_LSB) #define GTYE3_CH_RXDFE_H3_CFG1_ADDR 0x00B0 #define GTYE3_CH_RXDFE_H3_CFG1_MSB 15 #define GTYE3_CH_RXDFE_H3_CFG1_LSB 0 #define GTYE3_CH_RXDFE_H3_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_H3_CFG1_MSB, GTYE3_CH_RXDFE_H3_CFG1_LSB) #define GTYE3_CH_RXDFE_H4_CFG0_ADDR 0x00B1 #define GTYE3_CH_RXDFE_H4_CFG0_MSB 15 #define GTYE3_CH_RXDFE_H4_CFG0_LSB 0 #define GTYE3_CH_RXDFE_H4_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_H4_CFG0_MSB, GTYE3_CH_RXDFE_H4_CFG0_LSB) #define GTYE3_CH_RXDFE_H4_CFG1_ADDR 0x00B2 #define GTYE3_CH_RXDFE_H4_CFG1_MSB 15 #define GTYE3_CH_RXDFE_H4_CFG1_LSB 0 #define GTYE3_CH_RXDFE_H4_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_H4_CFG1_MSB, GTYE3_CH_RXDFE_H4_CFG1_LSB) #define GTYE3_CH_RXDFE_H5_CFG0_ADDR 0x00B3 #define GTYE3_CH_RXDFE_H5_CFG0_MSB 15 #define GTYE3_CH_RXDFE_H5_CFG0_LSB 0 #define GTYE3_CH_RXDFE_H5_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_H5_CFG0_MSB, GTYE3_CH_RXDFE_H5_CFG0_LSB) #define GTYE3_CH_PROCESS_PAR_ADDR 0x00B4 #define GTYE3_CH_PROCESS_PAR_MSB 15 #define GTYE3_CH_PROCESS_PAR_LSB 13 #define GTYE3_CH_PROCESS_PAR_MASK BIT_MASK(GTYE3_CH_PROCESS_PAR_MSB, GTYE3_CH_PROCESS_PAR_LSB) #define GTYE3_CH_TEMPERATURE_PAR_ADDR 0x00B4 #define GTYE3_CH_TEMPERATURE_PAR_MSB 11 #define GTYE3_CH_TEMPERATURE_PAR_LSB 8 #define GTYE3_CH_TEMPERATURE_PAR_MASK BIT_MASK(GTYE3_CH_TEMPERATURE_PAR_MSB, GTYE3_CH_TEMPERATURE_PAR_LSB) #define GTYE3_CH_TX_MODE_SEL_ADDR 0x00B4 #define GTYE3_CH_TX_MODE_SEL_MSB 7 #define GTYE3_CH_TX_MODE_SEL_LSB 5 #define GTYE3_CH_TX_MODE_SEL_MASK BIT_MASK(GTYE3_CH_TX_MODE_SEL_MSB, GTYE3_CH_TX_MODE_SEL_LSB) #define GTYE3_CH_TX_SARC_LPBK_ENB_ADDR 0x00B4 #define GTYE3_CH_TX_SARC_LPBK_ENB_MSB 4 #define GTYE3_CH_TX_SARC_LPBK_ENB_LSB 4 #define GTYE3_CH_TX_SARC_LPBK_ENB_MASK BIT_MASK(GTYE3_CH_TX_SARC_LPBK_ENB_MSB, GTYE3_CH_TX_SARC_LPBK_ENB_LSB) #define GTYE3_CH_RXDFE_H5_CFG1_ADDR 0x00B5 #define GTYE3_CH_RXDFE_H5_CFG1_MSB 15 #define GTYE3_CH_RXDFE_H5_CFG1_LSB 0 #define GTYE3_CH_RXDFE_H5_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_H5_CFG1_MSB, GTYE3_CH_RXDFE_H5_CFG1_LSB) #define GTYE3_CH_TX_DCD_CFG_ADDR 0x00B6 #define GTYE3_CH_TX_DCD_CFG_MSB 15 #define GTYE3_CH_TX_DCD_CFG_LSB 10 #define GTYE3_CH_TX_DCD_CFG_MASK BIT_MASK(GTYE3_CH_TX_DCD_CFG_MSB, GTYE3_CH_TX_DCD_CFG_LSB) #define GTYE3_CH_TX_DCD_EN_ADDR 0x00B6 #define GTYE3_CH_TX_DCD_EN_MSB 9 #define GTYE3_CH_TX_DCD_EN_LSB 9 #define GTYE3_CH_TX_DCD_EN_MASK BIT_MASK(GTYE3_CH_TX_DCD_EN_MSB, GTYE3_CH_TX_DCD_EN_LSB) #define GTYE3_CH_TX_EML_PHI_TUNE_ADDR 0x00B6 #define GTYE3_CH_TX_EML_PHI_TUNE_MSB 8 #define GTYE3_CH_TX_EML_PHI_TUNE_LSB 8 #define GTYE3_CH_TX_EML_PHI_TUNE_MASK BIT_MASK(GTYE3_CH_TX_EML_PHI_TUNE_MSB, GTYE3_CH_TX_EML_PHI_TUNE_LSB) #define GTYE3_CH_CPLL_CFG3_ADDR 0x00B6 #define GTYE3_CH_CPLL_CFG3_MSB 5 #define GTYE3_CH_CPLL_CFG3_LSB 0 #define GTYE3_CH_CPLL_CFG3_MASK BIT_MASK(GTYE3_CH_CPLL_CFG3_MSB, GTYE3_CH_CPLL_CFG3_LSB) #define GTYE3_CH_RXDFE_H6_CFG0_ADDR 0x00B7 #define GTYE3_CH_RXDFE_H6_CFG0_MSB 15 #define GTYE3_CH_RXDFE_H6_CFG0_LSB 0 #define GTYE3_CH_RXDFE_H6_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_H6_CFG0_MSB, GTYE3_CH_RXDFE_H6_CFG0_LSB) #define GTYE3_CH_RXDFE_H6_CFG1_ADDR 0x00B8 #define GTYE3_CH_RXDFE_H6_CFG1_MSB 15 #define GTYE3_CH_RXDFE_H6_CFG1_LSB 0 #define GTYE3_CH_RXDFE_H6_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_H6_CFG1_MSB, GTYE3_CH_RXDFE_H6_CFG1_LSB) #define GTYE3_CH_RXDFE_H7_CFG0_ADDR 0x00B9 #define GTYE3_CH_RXDFE_H7_CFG0_MSB 15 #define GTYE3_CH_RXDFE_H7_CFG0_LSB 0 #define GTYE3_CH_RXDFE_H7_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_H7_CFG0_MSB, GTYE3_CH_RXDFE_H7_CFG0_LSB) #define GTYE3_CH_DDI_REALIGN_WAIT_ADDR 0x00BA #define GTYE3_CH_DDI_REALIGN_WAIT_MSB 6 #define GTYE3_CH_DDI_REALIGN_WAIT_LSB 2 #define GTYE3_CH_DDI_REALIGN_WAIT_MASK BIT_MASK(GTYE3_CH_DDI_REALIGN_WAIT_MSB, GTYE3_CH_DDI_REALIGN_WAIT_LSB) #define GTYE3_CH_DDI_CTRL_ADDR 0x00BA #define GTYE3_CH_DDI_CTRL_MSB 1 #define GTYE3_CH_DDI_CTRL_LSB 0 #define GTYE3_CH_DDI_CTRL_MASK BIT_MASK(GTYE3_CH_DDI_CTRL_MSB, GTYE3_CH_DDI_CTRL_LSB) #define GTYE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_ADDR 0x00BB #define GTYE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_MSB 11 #define GTYE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_LSB 9 #define GTYE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_MASK BIT_MASK(GTYE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_MSB, GTYE3_CH_TXGBOX_FIFO_INIT_RD_ADDR_LSB) #define GTYE3_CH_TX_SAMPLE_PERIOD_ADDR 0x00BB #define GTYE3_CH_TX_SAMPLE_PERIOD_MSB 8 #define GTYE3_CH_TX_SAMPLE_PERIOD_LSB 6 #define GTYE3_CH_TX_SAMPLE_PERIOD_MASK BIT_MASK(GTYE3_CH_TX_SAMPLE_PERIOD_MSB, GTYE3_CH_TX_SAMPLE_PERIOD_LSB) #define GTYE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_ADDR 0x00BB #define GTYE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_MSB 5 #define GTYE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_LSB 3 #define GTYE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_MASK BIT_MASK(GTYE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_MSB, GTYE3_CH_RXGBOX_FIFO_INIT_RD_ADDR_LSB) #define GTYE3_CH_RX_SAMPLE_PERIOD_ADDR 0x00BB #define GTYE3_CH_RX_SAMPLE_PERIOD_MSB 2 #define GTYE3_CH_RX_SAMPLE_PERIOD_LSB 0 #define GTYE3_CH_RX_SAMPLE_PERIOD_MASK BIT_MASK(GTYE3_CH_RX_SAMPLE_PERIOD_MSB, GTYE3_CH_RX_SAMPLE_PERIOD_LSB) #define GTYE3_CH_CPLL_CFG2_ADDR 0x00BC #define GTYE3_CH_CPLL_CFG2_MSB 15 #define GTYE3_CH_CPLL_CFG2_LSB 0 #define GTYE3_CH_CPLL_CFG2_MASK BIT_MASK(GTYE3_CH_CPLL_CFG2_MSB, GTYE3_CH_CPLL_CFG2_LSB) #define GTYE3_CH_RXPHSAMP_CFG_ADDR 0x00BD #define GTYE3_CH_RXPHSAMP_CFG_MSB 15 #define GTYE3_CH_RXPHSAMP_CFG_LSB 0 #define GTYE3_CH_RXPHSAMP_CFG_MASK BIT_MASK(GTYE3_CH_RXPHSAMP_CFG_MSB, GTYE3_CH_RXPHSAMP_CFG_LSB) #define GTYE3_CH_RXPHSLIP_CFG_ADDR 0x00BE #define GTYE3_CH_RXPHSLIP_CFG_MSB 15 #define GTYE3_CH_RXPHSLIP_CFG_LSB 0 #define GTYE3_CH_RXPHSLIP_CFG_MASK BIT_MASK(GTYE3_CH_RXPHSLIP_CFG_MSB, GTYE3_CH_RXPHSLIP_CFG_LSB) #define GTYE3_CH_RXPHBEACON_CFG_ADDR 0x00BF #define GTYE3_CH_RXPHBEACON_CFG_MSB 15 #define GTYE3_CH_RXPHBEACON_CFG_LSB 0 #define GTYE3_CH_RXPHBEACON_CFG_MASK BIT_MASK(GTYE3_CH_RXPHBEACON_CFG_MSB, GTYE3_CH_RXPHBEACON_CFG_LSB) #define GTYE3_CH_RXDFE_H7_CFG1_ADDR 0x00C0 #define GTYE3_CH_RXDFE_H7_CFG1_MSB 15 #define GTYE3_CH_RXDFE_H7_CFG1_LSB 0 #define GTYE3_CH_RXDFE_H7_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_H7_CFG1_MSB, GTYE3_CH_RXDFE_H7_CFG1_LSB) #define GTYE3_CH_RXDFE_H8_CFG0_ADDR 0x00C1 #define GTYE3_CH_RXDFE_H8_CFG0_MSB 15 #define GTYE3_CH_RXDFE_H8_CFG0_LSB 0 #define GTYE3_CH_RXDFE_H8_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_H8_CFG0_MSB, GTYE3_CH_RXDFE_H8_CFG0_LSB) #define GTYE3_CH_RXDFE_H8_CFG1_ADDR 0x00C2 #define GTYE3_CH_RXDFE_H8_CFG1_MSB 15 #define GTYE3_CH_RXDFE_H8_CFG1_LSB 0 #define GTYE3_CH_RXDFE_H8_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_H8_CFG1_MSB, GTYE3_CH_RXDFE_H8_CFG1_LSB) #define GTYE3_CH_PCIE_BUFG_DIV_CTRL_ADDR 0x00C3 #define GTYE3_CH_PCIE_BUFG_DIV_CTRL_MSB 15 #define GTYE3_CH_PCIE_BUFG_DIV_CTRL_LSB 0 #define GTYE3_CH_PCIE_BUFG_DIV_CTRL_MASK BIT_MASK(GTYE3_CH_PCIE_BUFG_DIV_CTRL_MSB, GTYE3_CH_PCIE_BUFG_DIV_CTRL_LSB) #define GTYE3_CH_PCIE_RXPCS_CFG_GEN3_ADDR 0x00C4 #define GTYE3_CH_PCIE_RXPCS_CFG_GEN3_MSB 15 #define GTYE3_CH_PCIE_RXPCS_CFG_GEN3_LSB 0 #define GTYE3_CH_PCIE_RXPCS_CFG_GEN3_MASK BIT_MASK(GTYE3_CH_PCIE_RXPCS_CFG_GEN3_MSB, GTYE3_CH_PCIE_RXPCS_CFG_GEN3_LSB) #define GTYE3_CH_RXDFE_H9_CFG0_ADDR 0x00C5 #define GTYE3_CH_RXDFE_H9_CFG0_MSB 15 #define GTYE3_CH_RXDFE_H9_CFG0_LSB 0 #define GTYE3_CH_RXDFE_H9_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_H9_CFG0_MSB, GTYE3_CH_RXDFE_H9_CFG0_LSB) #define GTYE3_CH_RX_PROGDIV_CFG_ADDR 0x00C6 #define GTYE3_CH_RX_PROGDIV_CFG_MSB 15 #define GTYE3_CH_RX_PROGDIV_CFG_LSB 0 #define GTYE3_CH_RX_PROGDIV_CFG_MASK BIT_MASK(GTYE3_CH_RX_PROGDIV_CFG_MSB, GTYE3_CH_RX_PROGDIV_CFG_LSB) #define GTYE3_CH_RX_PROGDIV_CFG_0 32768 #define GTYE3_CH_RX_PROGDIV_CFG_4 57744 #define GTYE3_CH_RX_PROGDIV_CFG_5 49648 #define GTYE3_CH_RX_PROGDIV_CFG_8 57728 #define GTYE3_CH_RX_PROGDIV_CFG_10 57760 #define GTYE3_CH_RX_PROGDIV_CFG_16 57730 #define GTYE3_CH_RX_PROGDIV_CFG_16P5 49672 #define GTYE3_CH_RX_PROGDIV_CFG_20 57762 #define GTYE3_CH_RX_PROGDIV_CFG_32 57734 #define GTYE3_CH_RX_PROGDIV_CFG_33 49800 #define GTYE3_CH_RX_PROGDIV_CFG_40 57766 #define GTYE3_CH_RX_PROGDIV_CFG_64 57742 #define GTYE3_CH_RX_PROGDIV_CFG_66 50056 #define GTYE3_CH_RX_PROGDIV_CFG_80 57743 #define GTYE3_CH_RX_PROGDIV_CFG_100 57775 #define GTYE3_CH_RXDFE_H9_CFG1_ADDR 0x00C7 #define GTYE3_CH_RXDFE_H9_CFG1_MSB 15 #define GTYE3_CH_RXDFE_H9_CFG1_LSB 0 #define GTYE3_CH_RXDFE_H9_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_H9_CFG1_MSB, GTYE3_CH_RXDFE_H9_CFG1_LSB) #define GTYE3_CH_RXDFE_HA_CFG0_ADDR 0x00C8 #define GTYE3_CH_RXDFE_HA_CFG0_MSB 15 #define GTYE3_CH_RXDFE_HA_CFG0_LSB 0 #define GTYE3_CH_RXDFE_HA_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_HA_CFG0_MSB, GTYE3_CH_RXDFE_HA_CFG0_LSB) #define GTYE3_CH_CHAN_BOND_SEQ_1_2_ADDR 0x00CA #define GTYE3_CH_CHAN_BOND_SEQ_1_2_MSB 9 #define GTYE3_CH_CHAN_BOND_SEQ_1_2_LSB 0 #define GTYE3_CH_CHAN_BOND_SEQ_1_2_MASK BIT_MASK(GTYE3_CH_CHAN_BOND_SEQ_1_2_MSB, GTYE3_CH_CHAN_BOND_SEQ_1_2_LSB) #define GTYE3_CH_CPLL_CFG0_ADDR 0x00CB #define GTYE3_CH_CPLL_CFG0_MSB 15 #define GTYE3_CH_CPLL_CFG0_LSB 0 #define GTYE3_CH_CPLL_CFG0_MASK BIT_MASK(GTYE3_CH_CPLL_CFG0_MSB, GTYE3_CH_CPLL_CFG0_LSB) #define GTYE3_CH_CPLL_CFG1_ADDR 0x00CC #define GTYE3_CH_CPLL_CFG1_MSB 15 #define GTYE3_CH_CPLL_CFG1_LSB 0 #define GTYE3_CH_CPLL_CFG1_MASK BIT_MASK(GTYE3_CH_CPLL_CFG1_MSB, GTYE3_CH_CPLL_CFG1_LSB) #define GTYE3_CH_CPLL_INIT_CFG1_ADDR 0x00CD #define GTYE3_CH_CPLL_INIT_CFG1_MSB 15 #define GTYE3_CH_CPLL_INIT_CFG1_LSB 8 #define GTYE3_CH_CPLL_INIT_CFG1_MASK BIT_MASK(GTYE3_CH_CPLL_INIT_CFG1_MSB, GTYE3_CH_CPLL_INIT_CFG1_LSB) #define GTYE3_CH_RX_DDI_SEL_ADDR 0x00CD #define GTYE3_CH_RX_DDI_SEL_MSB 7 #define GTYE3_CH_RX_DDI_SEL_LSB 2 #define GTYE3_CH_RX_DDI_SEL_MASK BIT_MASK(GTYE3_CH_RX_DDI_SEL_MSB, GTYE3_CH_RX_DDI_SEL_LSB) #define GTYE3_CH_DEC_VALID_COMMA_ONLY_ADDR 0x00CD #define GTYE3_CH_DEC_VALID_COMMA_ONLY_MSB 1 #define GTYE3_CH_DEC_VALID_COMMA_ONLY_LSB 1 #define GTYE3_CH_DEC_VALID_COMMA_ONLY_MASK BIT_MASK(GTYE3_CH_DEC_VALID_COMMA_ONLY_MSB, GTYE3_CH_DEC_VALID_COMMA_ONLY_LSB) #define GTYE3_CH_DEC_MCOMMA_DETECT_ADDR 0x00CD #define GTYE3_CH_DEC_MCOMMA_DETECT_MSB 0 #define GTYE3_CH_DEC_MCOMMA_DETECT_LSB 0 #define GTYE3_CH_DEC_MCOMMA_DETECT_MASK BIT_MASK(GTYE3_CH_DEC_MCOMMA_DETECT_MSB, GTYE3_CH_DEC_MCOMMA_DETECT_LSB) #define GTYE3_CH_RXDFE_HA_CFG1_ADDR 0x00CE #define GTYE3_CH_RXDFE_HA_CFG1_MSB 15 #define GTYE3_CH_RXDFE_HA_CFG1_LSB 0 #define GTYE3_CH_RXDFE_HA_CFG1_MASK BIT_MASK(GTYE3_CH_RXDFE_HA_CFG1_MSB, GTYE3_CH_RXDFE_HA_CFG1_LSB) #define GTYE3_CH_RXDFE_HB_CFG0_ADDR 0x00CF #define GTYE3_CH_RXDFE_HB_CFG0_MSB 15 #define GTYE3_CH_RXDFE_HB_CFG0_LSB 0 #define GTYE3_CH_RXDFE_HB_CFG0_MASK BIT_MASK(GTYE3_CH_RXDFE_HB_CFG0_MSB, GTYE3_CH_RXDFE_HB_CFG0_LSB) #define GTYE3_CH_RX_DEGEN_CTRL_ADDR 0x00D0 #define GTYE3_CH_RX_DEGEN_CTRL_MSB 6 #define GTYE3_CH_RX_DEGEN_CTRL_LSB 4 #define GTYE3_CH_RX_DEGEN_CTRL_MASK BIT_MASK(GTYE3_CH_RX_DEGEN_CTRL_MSB, GTYE3_CH_RX_DEGEN_CTRL_LSB) #define GTYE3_CH_RX_RESLOAD_CTRL_ADDR 0x00D0 #define GTYE3_CH_RX_RESLOAD_CTRL_MSB 3 #define GTYE3_CH_RX_RESLOAD_CTRL_LSB 0 #define GTYE3_CH_RX_RESLOAD_CTRL_MASK BIT_MASK(GTYE3_CH_RX_RESLOAD_CTRL_MSB, GTYE3_CH_RX_RESLOAD_CTRL_LSB) #define GTYE3_CH_RX_RESLOAD_OVRD_ADDR 0x00D0 #define GTYE3_CH_RX_RESLOAD_OVRD_MSB 8 #define GTYE3_CH_RX_RESLOAD_OVRD_LSB 8 #define GTYE3_CH_RX_RESLOAD_OVRD_MASK BIT_MASK(GTYE3_CH_RX_RESLOAD_OVRD_MSB, GTYE3_CH_RX_RESLOAD_OVRD_LSB) #define GTYE3_CH_RX_EN_CTLE_RCAL_B_ADDR 0x00D1 #define GTYE3_CH_RX_EN_CTLE_RCAL_B_MSB 12 #define GTYE3_CH_RX_EN_CTLE_RCAL_B_LSB 12 #define GTYE3_CH_RX_EN_CTLE_RCAL_B_MASK BIT_MASK(GTYE3_CH_RX_EN_CTLE_RCAL_B_MSB, GTYE3_CH_RX_EN_CTLE_RCAL_B_LSB) #define GTYE3_CH_RX_EXT_RL_CTRL_ADDR 0x00D1 #define GTYE3_CH_RX_EXT_RL_CTRL_MSB 11 #define GTYE3_CH_RX_EXT_RL_CTRL_LSB 3 #define GTYE3_CH_RX_EXT_RL_CTRL_MASK BIT_MASK(GTYE3_CH_RX_EXT_RL_CTRL_MSB, GTYE3_CH_RX_EXT_RL_CTRL_LSB) #define GTYE3_CH_RX_CTLE1_KHKL_ADDR 0x00D1 #define GTYE3_CH_RX_CTLE1_KHKL_MSB 2 #define GTYE3_CH_RX_CTLE1_KHKL_LSB 2 #define GTYE3_CH_RX_CTLE1_KHKL_MASK BIT_MASK(GTYE3_CH_RX_CTLE1_KHKL_MSB, GTYE3_CH_RX_CTLE1_KHKL_LSB) #define GTYE3_CH_RX_CTLE2_KHKL_ADDR 0x00D1 #define GTYE3_CH_RX_CTLE2_KHKL_MSB 1 #define GTYE3_CH_RX_CTLE2_KHKL_LSB 1 #define GTYE3_CH_RX_CTLE2_KHKL_MASK BIT_MASK(GTYE3_CH_RX_CTLE2_KHKL_MSB, GTYE3_CH_RX_CTLE2_KHKL_LSB) #define GTYE3_CH_RX_CTLE3_AGC_ADDR 0x00D1 #define GTYE3_CH_RX_CTLE3_AGC_MSB 0 #define GTYE3_CH_RX_CTLE3_AGC_LSB 0 #define GTYE3_CH_RX_CTLE3_AGC_MASK BIT_MASK(GTYE3_CH_RX_CTLE3_AGC_MSB, GTYE3_CH_RX_CTLE3_AGC_LSB) #define GTYE3_CH_LPBK_EN_RCAL_B_ADDR 0x00D3 #define GTYE3_CH_LPBK_EN_RCAL_B_MSB 13 #define GTYE3_CH_LPBK_EN_RCAL_B_LSB 13 #define GTYE3_CH_LPBK_EN_RCAL_B_MASK BIT_MASK(GTYE3_CH_LPBK_EN_RCAL_B_MSB, GTYE3_CH_LPBK_EN_RCAL_B_LSB) #define GTYE3_CH_LPBK_BIAS_CTRL_ADDR 0x00D3 #define GTYE3_CH_LPBK_BIAS_CTRL_MSB 4 #define GTYE3_CH_LPBK_BIAS_CTRL_LSB 2 #define GTYE3_CH_LPBK_BIAS_CTRL_MASK BIT_MASK(GTYE3_CH_LPBK_BIAS_CTRL_MSB, GTYE3_CH_LPBK_BIAS_CTRL_LSB) #define GTYE3_CH_RX_XMODE_SEL_ADDR 0x00D3 #define GTYE3_CH_RX_XMODE_SEL_MSB 1 #define GTYE3_CH_RX_XMODE_SEL_LSB 1 #define GTYE3_CH_RX_XMODE_SEL_MASK BIT_MASK(GTYE3_CH_RX_XMODE_SEL_MSB, GTYE3_CH_RX_XMODE_SEL_LSB) #define GTYE3_CH_ISCAN_CK_PH_SEL2_ADDR 0x00D3 #define GTYE3_CH_ISCAN_CK_PH_SEL2_MSB 0 #define GTYE3_CH_ISCAN_CK_PH_SEL2_LSB 0 #define GTYE3_CH_ISCAN_CK_PH_SEL2_MASK BIT_MASK(GTYE3_CH_ISCAN_CK_PH_SEL2_MSB, GTYE3_CH_ISCAN_CK_PH_SEL2_LSB) #define GTYE3_CH_LPBK_RG_CTRL_ADDR 0x00D4 #define GTYE3_CH_LPBK_RG_CTRL_MSB 10 #define GTYE3_CH_LPBK_RG_CTRL_LSB 7 #define GTYE3_CH_LPBK_RG_CTRL_MASK BIT_MASK(GTYE3_CH_LPBK_RG_CTRL_MSB, GTYE3_CH_LPBK_RG_CTRL_LSB) #define GTYE3_CH_TX_PI_SEL_QPLL1_ADDR 0x00D4 #define GTYE3_CH_TX_PI_SEL_QPLL1_MSB 6 #define GTYE3_CH_TX_PI_SEL_QPLL1_LSB 6 #define GTYE3_CH_TX_PI_SEL_QPLL1_MASK BIT_MASK(GTYE3_CH_TX_PI_SEL_QPLL1_MSB, GTYE3_CH_TX_PI_SEL_QPLL1_LSB) #define GTYE3_CH_TX_PI_SEL_QPLL0_ADDR 0x00D4 #define GTYE3_CH_TX_PI_SEL_QPLL0_MSB 5 #define GTYE3_CH_TX_PI_SEL_QPLL0_LSB 5 #define GTYE3_CH_TX_PI_SEL_QPLL0_MASK BIT_MASK(GTYE3_CH_TX_PI_SEL_QPLL0_MSB, GTYE3_CH_TX_PI_SEL_QPLL0_LSB) #define GTYE3_CH_CKCAL1_CFG_0_ADDR 0x00D5 #define GTYE3_CH_CKCAL1_CFG_0_MSB 15 #define GTYE3_CH_CKCAL1_CFG_0_LSB 0 #define GTYE3_CH_CKCAL1_CFG_0_MASK BIT_MASK(GTYE3_CH_CKCAL1_CFG_0_MSB, GTYE3_CH_CKCAL1_CFG_0_LSB) #define GTYE3_CH_CKCAL1_CFG_1_ADDR 0x00D6 #define GTYE3_CH_CKCAL1_CFG_1_MSB 15 #define GTYE3_CH_CKCAL1_CFG_1_LSB 0 #define GTYE3_CH_CKCAL1_CFG_1_MASK BIT_MASK(GTYE3_CH_CKCAL1_CFG_1_MSB, GTYE3_CH_CKCAL1_CFG_1_LSB) #define GTYE3_CH_CKCAL2_CFG_0_ADDR 0x00D7 #define GTYE3_CH_CKCAL2_CFG_0_MSB 15 #define GTYE3_CH_CKCAL2_CFG_0_LSB 0 #define GTYE3_CH_CKCAL2_CFG_0_MASK BIT_MASK(GTYE3_CH_CKCAL2_CFG_0_MSB, GTYE3_CH_CKCAL2_CFG_0_LSB) #define GTYE3_CH_CKCAL2_CFG_1_ADDR 0x00D8 #define GTYE3_CH_CKCAL2_CFG_1_MSB 15 #define GTYE3_CH_CKCAL2_CFG_1_LSB 0 #define GTYE3_CH_CKCAL2_CFG_1_MASK BIT_MASK(GTYE3_CH_CKCAL2_CFG_1_MSB, GTYE3_CH_CKCAL2_CFG_1_LSB) #define GTYE3_CH_CKCAL2_CFG_2_ADDR 0x00D9 #define GTYE3_CH_CKCAL2_CFG_2_MSB 15 #define GTYE3_CH_CKCAL2_CFG_2_LSB 0 #define GTYE3_CH_CKCAL2_CFG_2_MASK BIT_MASK(GTYE3_CH_CKCAL2_CFG_2_MSB, GTYE3_CH_CKCAL2_CFG_2_LSB) #define GTYE3_CH_ADAPT_CFG2_ADDR 0x00DA #define GTYE3_CH_ADAPT_CFG2_MSB 15 #define GTYE3_CH_ADAPT_CFG2_LSB 0 #define GTYE3_CH_ADAPT_CFG2_MASK BIT_MASK(GTYE3_CH_ADAPT_CFG2_MSB, GTYE3_CH_ADAPT_CFG2_LSB) #define GTYE3_CH_RXCDR_LOCK_CFG3_ADDR 0x00DB #define GTYE3_CH_RXCDR_LOCK_CFG3_MSB 15 #define GTYE3_CH_RXCDR_LOCK_CFG3_LSB 0 #define GTYE3_CH_RXCDR_LOCK_CFG3_MASK BIT_MASK(GTYE3_CH_RXCDR_LOCK_CFG3_MSB, GTYE3_CH_RXCDR_LOCK_CFG3_LSB) #define GTYE3_CH_TXPH_CFG2_ADDR 0x00DE #define GTYE3_CH_TXPH_CFG2_MSB 15 #define GTYE3_CH_TXPH_CFG2_LSB 0 #define GTYE3_CH_TXPH_CFG2_MASK BIT_MASK(GTYE3_CH_TXPH_CFG2_MSB, GTYE3_CH_TXPH_CFG2_LSB) #define GTYE3_CH_AUTO_BW_SEL_BYPASS_ADDR 0x00DF #define GTYE3_CH_AUTO_BW_SEL_BYPASS_MSB 0 #define GTYE3_CH_AUTO_BW_SEL_BYPASS_LSB 0 #define GTYE3_CH_AUTO_BW_SEL_BYPASS_MASK BIT_MASK(GTYE3_CH_AUTO_BW_SEL_BYPASS_MSB, GTYE3_CH_AUTO_BW_SEL_BYPASS_LSB) #define GTYE3_CH_RXDFE_PWR_SAVING_ADDR 0x00E0 #define GTYE3_CH_RXDFE_PWR_SAVING_MSB 9 #define GTYE3_CH_RXDFE_PWR_SAVING_LSB 9 #define GTYE3_CH_RXDFE_PWR_SAVING_MASK BIT_MASK(GTYE3_CH_RXDFE_PWR_SAVING_MSB, GTYE3_CH_RXDFE_PWR_SAVING_LSB) #define GTYE3_CH_CTLE3_OCAP_EXT_CTRL_ADDR 0x00E0 #define GTYE3_CH_CTLE3_OCAP_EXT_CTRL_MSB 8 #define GTYE3_CH_CTLE3_OCAP_EXT_CTRL_LSB 6 #define GTYE3_CH_CTLE3_OCAP_EXT_CTRL_MASK BIT_MASK(GTYE3_CH_CTLE3_OCAP_EXT_CTRL_MSB, GTYE3_CH_CTLE3_OCAP_EXT_CTRL_LSB) #define GTYE3_CH_CTLE3_OCAP_EXT_EN_ADDR 0x00E0 #define GTYE3_CH_CTLE3_OCAP_EXT_EN_MSB 5 #define GTYE3_CH_CTLE3_OCAP_EXT_EN_LSB 5 #define GTYE3_CH_CTLE3_OCAP_EXT_EN_MASK BIT_MASK(GTYE3_CH_CTLE3_OCAP_EXT_EN_MSB, GTYE3_CH_CTLE3_OCAP_EXT_EN_LSB) #define GTYE3_CH_RXPI_STARTCODE_ADDR 0x00E0 #define GTYE3_CH_RXPI_STARTCODE_MSB 1 #define GTYE3_CH_RXPI_STARTCODE_LSB 0 #define GTYE3_CH_RXPI_STARTCODE_MASK BIT_MASK(GTYE3_CH_RXPI_STARTCODE_MSB, GTYE3_CH_RXPI_STARTCODE_LSB) #define GTYE3_CH_CAPBYPASS_FORCE_ADDR 0x00E1 #define GTYE3_CH_CAPBYPASS_FORCE_MSB 0 #define GTYE3_CH_CAPBYPASS_FORCE_LSB 0 #define GTYE3_CH_CAPBYPASS_FORCE_MASK BIT_MASK(GTYE3_CH_CAPBYPASS_FORCE_MSB, GTYE3_CH_CAPBYPASS_FORCE_LSB) #define GTYE3_CH_TX_PREDRV_CTRL_ADDR 0x00E2 #define GTYE3_CH_TX_PREDRV_CTRL_MSB 7 #define GTYE3_CH_TX_PREDRV_CTRL_LSB 6 #define GTYE3_CH_TX_PREDRV_CTRL_MASK BIT_MASK(GTYE3_CH_TX_PREDRV_CTRL_MSB, GTYE3_CH_TX_PREDRV_CTRL_LSB) #define GTYE3_CH_TX_DRVMUX_CTRL_ADDR 0x00E2 #define GTYE3_CH_TX_DRVMUX_CTRL_MSB 5 #define GTYE3_CH_TX_DRVMUX_CTRL_LSB 4 #define GTYE3_CH_TX_DRVMUX_CTRL_MASK BIT_MASK(GTYE3_CH_TX_DRVMUX_CTRL_MSB, GTYE3_CH_TX_DRVMUX_CTRL_LSB) #define GTYE3_CH_TX_CLKREG_SET_ADDR 0x00E2 #define GTYE3_CH_TX_CLKREG_SET_MSB 3 #define GTYE3_CH_TX_CLKREG_SET_LSB 1 #define GTYE3_CH_TX_CLKREG_SET_MASK BIT_MASK(GTYE3_CH_TX_CLKREG_SET_MSB, GTYE3_CH_TX_CLKREG_SET_LSB) #define GTYE3_CH_TX_CLKREG_PDB_ADDR 0x00E2 #define GTYE3_CH_TX_CLKREG_PDB_MSB 0 #define GTYE3_CH_TX_CLKREG_PDB_LSB 0 #define GTYE3_CH_TX_CLKREG_PDB_MASK BIT_MASK(GTYE3_CH_TX_CLKREG_PDB_MSB, GTYE3_CH_TX_CLKREG_PDB_LSB) #define GTYE3_CH_ES_QUALIFIER5_ADDR 0x00E7 #define GTYE3_CH_ES_QUALIFIER5_MSB 15 #define GTYE3_CH_ES_QUALIFIER5_LSB 0 #define GTYE3_CH_ES_QUALIFIER5_MASK BIT_MASK(GTYE3_CH_ES_QUALIFIER5_MSB, GTYE3_CH_ES_QUALIFIER5_LSB) #define GTYE3_CH_ES_QUALIFIER6_ADDR 0x00E8 #define GTYE3_CH_ES_QUALIFIER6_MSB 15 #define GTYE3_CH_ES_QUALIFIER6_LSB 0 #define GTYE3_CH_ES_QUALIFIER6_MASK BIT_MASK(GTYE3_CH_ES_QUALIFIER6_MSB, GTYE3_CH_ES_QUALIFIER6_LSB) #define GTYE3_CH_ES_QUALIFIER7_ADDR 0x00E9 #define GTYE3_CH_ES_QUALIFIER7_MSB 15 #define GTYE3_CH_ES_QUALIFIER7_LSB 0 #define GTYE3_CH_ES_QUALIFIER7_MASK BIT_MASK(GTYE3_CH_ES_QUALIFIER7_MSB, GTYE3_CH_ES_QUALIFIER7_LSB) #define GTYE3_CH_ES_QUALIFIER8_ADDR 0x00EA #define GTYE3_CH_ES_QUALIFIER8_MSB 15 #define GTYE3_CH_ES_QUALIFIER8_LSB 0 #define GTYE3_CH_ES_QUALIFIER8_MASK BIT_MASK(GTYE3_CH_ES_QUALIFIER8_MSB, GTYE3_CH_ES_QUALIFIER8_LSB) #define GTYE3_CH_ES_QUALIFIER9_ADDR 0x00EB #define GTYE3_CH_ES_QUALIFIER9_MSB 15 #define GTYE3_CH_ES_QUALIFIER9_LSB 0 #define GTYE3_CH_ES_QUALIFIER9_MASK BIT_MASK(GTYE3_CH_ES_QUALIFIER9_MSB, GTYE3_CH_ES_QUALIFIER9_LSB) #define GTYE3_CH_ES_QUAL_MASK5_ADDR 0x00EC #define GTYE3_CH_ES_QUAL_MASK5_MSB 15 #define GTYE3_CH_ES_QUAL_MASK5_LSB 0 #define GTYE3_CH_ES_QUAL_MASK5_MASK BIT_MASK(GTYE3_CH_ES_QUAL_MASK5_MSB, GTYE3_CH_ES_QUAL_MASK5_LSB) #define GTYE3_CH_ES_QUAL_MASK6_ADDR 0x00ED #define GTYE3_CH_ES_QUAL_MASK6_MSB 15 #define GTYE3_CH_ES_QUAL_MASK6_LSB 0 #define GTYE3_CH_ES_QUAL_MASK6_MASK BIT_MASK(GTYE3_CH_ES_QUAL_MASK6_MSB, GTYE3_CH_ES_QUAL_MASK6_LSB) #define GTYE3_CH_ES_QUAL_MASK7_ADDR 0x00EE #define GTYE3_CH_ES_QUAL_MASK7_MSB 15 #define GTYE3_CH_ES_QUAL_MASK7_LSB 0 #define GTYE3_CH_ES_QUAL_MASK7_MASK BIT_MASK(GTYE3_CH_ES_QUAL_MASK7_MSB, GTYE3_CH_ES_QUAL_MASK7_LSB) #define GTYE3_CH_ES_QUAL_MASK8_ADDR 0x00EF #define GTYE3_CH_ES_QUAL_MASK8_MSB 15 #define GTYE3_CH_ES_QUAL_MASK8_LSB 0 #define GTYE3_CH_ES_QUAL_MASK8_MASK BIT_MASK(GTYE3_CH_ES_QUAL_MASK8_MSB, GTYE3_CH_ES_QUAL_MASK8_LSB) #define GTYE3_CH_ES_QUAL_MASK9_ADDR 0x00F0 #define GTYE3_CH_ES_QUAL_MASK9_MSB 15 #define GTYE3_CH_ES_QUAL_MASK9_LSB 0 #define GTYE3_CH_ES_QUAL_MASK9_MASK BIT_MASK(GTYE3_CH_ES_QUAL_MASK9_MSB, GTYE3_CH_ES_QUAL_MASK9_LSB) #define GTYE3_CH_ES_SDATA_MASK5_ADDR 0x00F1 #define GTYE3_CH_ES_SDATA_MASK5_MSB 15 #define GTYE3_CH_ES_SDATA_MASK5_LSB 0 #define GTYE3_CH_ES_SDATA_MASK5_MASK BIT_MASK(GTYE3_CH_ES_SDATA_MASK5_MSB, GTYE3_CH_ES_SDATA_MASK5_LSB) #define GTYE3_CH_ES_SDATA_MASK6_ADDR 0x00F2 #define GTYE3_CH_ES_SDATA_MASK6_MSB 15 #define GTYE3_CH_ES_SDATA_MASK6_LSB 0 #define GTYE3_CH_ES_SDATA_MASK6_MASK BIT_MASK(GTYE3_CH_ES_SDATA_MASK6_MSB, GTYE3_CH_ES_SDATA_MASK6_LSB) #define GTYE3_CH_ES_SDATA_MASK7_ADDR 0x00F3 #define GTYE3_CH_ES_SDATA_MASK7_MSB 15 #define GTYE3_CH_ES_SDATA_MASK7_LSB 0 #define GTYE3_CH_ES_SDATA_MASK7_MASK BIT_MASK(GTYE3_CH_ES_SDATA_MASK7_MSB, GTYE3_CH_ES_SDATA_MASK7_LSB) #define GTYE3_CH_ES_SDATA_MASK8_ADDR 0x00F4 #define GTYE3_CH_ES_SDATA_MASK8_MSB 15 #define GTYE3_CH_ES_SDATA_MASK8_LSB 0 #define GTYE3_CH_ES_SDATA_MASK8_MASK BIT_MASK(GTYE3_CH_ES_SDATA_MASK8_MSB, GTYE3_CH_ES_SDATA_MASK8_LSB) #define GTYE3_CH_ES_SDATA_MASK9_ADDR 0x00F5 #define GTYE3_CH_ES_SDATA_MASK9_MSB 15 #define GTYE3_CH_ES_SDATA_MASK9_LSB 0 #define GTYE3_CH_ES_SDATA_MASK9_MASK BIT_MASK(GTYE3_CH_ES_SDATA_MASK9_MSB, GTYE3_CH_ES_SDATA_MASK9_LSB) #define GTYE3_CH_CKCAL1_CFG_3_ADDR 0x00F7 #define GTYE3_CH_CKCAL1_CFG_3_MSB 15 #define GTYE3_CH_CKCAL1_CFG_3_LSB 0 #define GTYE3_CH_CKCAL1_CFG_3_MASK BIT_MASK(GTYE3_CH_CKCAL1_CFG_3_MSB, GTYE3_CH_CKCAL1_CFG_3_LSB) #define GTYE3_CH_CKCAL2_CFG_3_ADDR 0x00F8 #define GTYE3_CH_CKCAL2_CFG_3_MSB 15 #define GTYE3_CH_CKCAL2_CFG_3_LSB 0 #define GTYE3_CH_CKCAL2_CFG_3_MASK BIT_MASK(GTYE3_CH_CKCAL2_CFG_3_MSB, GTYE3_CH_CKCAL2_CFG_3_LSB) #define GTYE3_CH_CKCAL2_CFG_4_ADDR 0x00F9 #define GTYE3_CH_CKCAL2_CFG_4_MSB 15 #define GTYE3_CH_CKCAL2_CFG_4_LSB 0 #define GTYE3_CH_CKCAL2_CFG_4_MASK BIT_MASK(GTYE3_CH_CKCAL2_CFG_4_MSB, GTYE3_CH_CKCAL2_CFG_4_LSB) #define GTYE3_CH_RX_DIV2_MODE_B_ADDR 0x00FA #define GTYE3_CH_RX_DIV2_MODE_B_MSB 5 #define GTYE3_CH_RX_DIV2_MODE_B_LSB 5 #define GTYE3_CH_RX_DIV2_MODE_B_MASK BIT_MASK(GTYE3_CH_RX_DIV2_MODE_B_MSB, GTYE3_CH_RX_DIV2_MODE_B_LSB) #define GTYE3_CH_RXPI_AUTO_BW_SEL_BYPASS_ADDR 0x00FA #define GTYE3_CH_RXPI_AUTO_BW_SEL_BYPASS_MSB 4 #define GTYE3_CH_RXPI_AUTO_BW_SEL_BYPASS_LSB 4 #define GTYE3_CH_RXPI_AUTO_BW_SEL_BYPASS_MASK BIT_MASK(GTYE3_CH_RXPI_AUTO_BW_SEL_BYPASS_MSB, GTYE3_CH_RXPI_AUTO_BW_SEL_BYPASS_LSB) #define GTYE3_CH_RX_VREG_CTRL_ADDR 0x00FA #define GTYE3_CH_RX_VREG_CTRL_MSB 3 #define GTYE3_CH_RX_VREG_CTRL_LSB 1 #define GTYE3_CH_RX_VREG_CTRL_MASK BIT_MASK(GTYE3_CH_RX_VREG_CTRL_MSB, GTYE3_CH_RX_VREG_CTRL_LSB) #define GTYE3_CH_RX_VREG_PDB_ADDR 0x00FA #define GTYE3_CH_RX_VREG_PDB_MSB 0 #define GTYE3_CH_RX_VREG_PDB_LSB 0 #define GTYE3_CH_RX_VREG_PDB_MASK BIT_MASK(GTYE3_CH_RX_VREG_PDB_MSB, GTYE3_CH_RX_VREG_PDB_LSB) #define GTYE3_CH_LPBK_EXT_RCAL_ADDR 0x00FB #define GTYE3_CH_LPBK_EXT_RCAL_MSB 9 #define GTYE3_CH_LPBK_EXT_RCAL_LSB 6 #define GTYE3_CH_LPBK_EXT_RCAL_MASK BIT_MASK(GTYE3_CH_LPBK_EXT_RCAL_MSB, GTYE3_CH_LPBK_EXT_RCAL_LSB) #define GTYE3_CH_PREIQ_FREQ_BST_ADDR 0x00FB #define GTYE3_CH_PREIQ_FREQ_BST_MSB 5 #define GTYE3_CH_PREIQ_FREQ_BST_LSB 4 #define GTYE3_CH_PREIQ_FREQ_BST_MASK BIT_MASK(GTYE3_CH_PREIQ_FREQ_BST_MSB, GTYE3_CH_PREIQ_FREQ_BST_LSB) #define GTYE3_CH_TX_FIFO_BYP_EN_ADDR 0x00FB #define GTYE3_CH_TX_FIFO_BYP_EN_MSB 3 #define GTYE3_CH_TX_FIFO_BYP_EN_LSB 3 #define GTYE3_CH_TX_FIFO_BYP_EN_MASK BIT_MASK(GTYE3_CH_TX_FIFO_BYP_EN_MSB, GTYE3_CH_TX_FIFO_BYP_EN_LSB) #define GTYE3_CH_TX_PI_BIASSET_ADDR 0x00FB #define GTYE3_CH_TX_PI_BIASSET_MSB 2 #define GTYE3_CH_TX_PI_BIASSET_LSB 1 #define GTYE3_CH_TX_PI_BIASSET_MASK BIT_MASK(GTYE3_CH_TX_PI_BIASSET_MSB, GTYE3_CH_TX_PI_BIASSET_LSB) #define GTYE3_CH_TX_PI_DIV2_MODE_B_ADDR 0x00FB #define GTYE3_CH_TX_PI_DIV2_MODE_B_MSB 0 #define GTYE3_CH_TX_PI_DIV2_MODE_B_LSB 0 #define GTYE3_CH_TX_PI_DIV2_MODE_B_MASK BIT_MASK(GTYE3_CH_TX_PI_DIV2_MODE_B_MSB, GTYE3_CH_TX_PI_DIV2_MODE_B_LSB) #define GTYE3_CH_TX_PHICAL_CFG0_ADDR 0x00FC #define GTYE3_CH_TX_PHICAL_CFG0_MSB 15 #define GTYE3_CH_TX_PHICAL_CFG0_LSB 0 #define GTYE3_CH_TX_PHICAL_CFG0_MASK BIT_MASK(GTYE3_CH_TX_PHICAL_CFG0_MSB, GTYE3_CH_TX_PHICAL_CFG0_LSB) #define GTYE3_CH_TX_PHICAL_CFG1_ADDR 0x00FD #define GTYE3_CH_TX_PHICAL_CFG1_MSB 15 #define GTYE3_CH_TX_PHICAL_CFG1_LSB 0 #define GTYE3_CH_TX_PHICAL_CFG1_MASK BIT_MASK(GTYE3_CH_TX_PHICAL_CFG1_MSB, GTYE3_CH_TX_PHICAL_CFG1_LSB) #define GTYE3_CH_TX_PHICAL_CFG2_ADDR 0x00FE #define GTYE3_CH_TX_PHICAL_CFG2_MSB 15 #define GTYE3_CH_TX_PHICAL_CFG2_LSB 0 #define GTYE3_CH_TX_PHICAL_CFG2_MASK BIT_MASK(GTYE3_CH_TX_PHICAL_CFG2_MSB, GTYE3_CH_TX_PHICAL_CFG2_LSB) #define GTYE3_CH_TX_PI_CFG0_ADDR 0x00FF #define GTYE3_CH_TX_PI_CFG0_MSB 15 #define GTYE3_CH_TX_PI_CFG0_LSB 0 #define GTYE3_CH_TX_PI_CFG0_MASK BIT_MASK(GTYE3_CH_TX_PI_CFG0_MSB, GTYE3_CH_TX_PI_CFG0_LSB) #define GTYE3_CH_TX_PI_CFG1_ADDR 0x0100 #define GTYE3_CH_TX_PI_CFG1_MSB 15 #define GTYE3_CH_TX_PI_CFG1_LSB 0 #define GTYE3_CH_TX_PI_CFG1_MASK BIT_MASK(GTYE3_CH_TX_PI_CFG1_MSB, GTYE3_CH_TX_PI_CFG1_LSB) #define GTYE3_CH_PMA_RSV0_ADDR 0x0101 #define GTYE3_CH_PMA_RSV0_MSB 15 #define GTYE3_CH_PMA_RSV0_LSB 0 #define GTYE3_CH_PMA_RSV0_MASK BIT_MASK(GTYE3_CH_PMA_RSV0_MSB, GTYE3_CH_PMA_RSV0_LSB) #define GTYE3_CH_RXPI_RSV0_ADDR 0x0102 #define GTYE3_CH_RXPI_RSV0_MSB 15 #define GTYE3_CH_RXPI_RSV0_LSB 0 #define GTYE3_CH_RXPI_RSV0_MASK BIT_MASK(GTYE3_CH_RXPI_RSV0_MSB, GTYE3_CH_RXPI_RSV0_LSB) #define GTYE3_CH_RX_PROGDIV_RATE_ADDR 0x0103 #define GTYE3_CH_RX_PROGDIV_RATE_MSB 15 #define GTYE3_CH_RX_PROGDIV_RATE_LSB 0 #define GTYE3_CH_RX_PROGDIV_RATE_MASK BIT_MASK(GTYE3_CH_RX_PROGDIV_RATE_MSB, GTYE3_CH_RX_PROGDIV_RATE_LSB) #define GTYE3_CH_RX_PROGDIV_RATE_HALF 0 #define GTYE3_CH_RX_PROGDIV_RATE_FULL 1 #define GTYE3_CH_TXPI_RSV0_ADDR 0x0104 #define GTYE3_CH_TXPI_RSV0_MSB 15 #define GTYE3_CH_TXPI_RSV0_LSB 0 #define GTYE3_CH_TXPI_RSV0_MASK BIT_MASK(GTYE3_CH_TXPI_RSV0_MSB, GTYE3_CH_TXPI_RSV0_LSB) #define GTYE3_CH_TX_PROGDIV_RATE_ADDR 0x0105 #define GTYE3_CH_TX_PROGDIV_RATE_MSB 15 #define GTYE3_CH_TX_PROGDIV_RATE_LSB 0 #define GTYE3_CH_TX_PROGDIV_RATE_MASK BIT_MASK(GTYE3_CH_TX_PROGDIV_RATE_MSB, GTYE3_CH_TX_PROGDIV_RATE_LSB) #define GTYE3_CH_TX_PROGDIV_RATE_HALF 0 #define GTYE3_CH_TX_PROGDIV_RATE_FULL 1 #define GTYE3_CH_LOOP0_CFG_ADDR 0x0106 #define GTYE3_CH_LOOP0_CFG_MSB 15 #define GTYE3_CH_LOOP0_CFG_LSB 0 #define GTYE3_CH_LOOP0_CFG_MASK BIT_MASK(GTYE3_CH_LOOP0_CFG_MSB, GTYE3_CH_LOOP0_CFG_LSB) #define GTYE3_CH_LOOP1_CFG_ADDR 0x0107 #define GTYE3_CH_LOOP1_CFG_MSB 15 #define GTYE3_CH_LOOP1_CFG_LSB 0 #define GTYE3_CH_LOOP1_CFG_MASK BIT_MASK(GTYE3_CH_LOOP1_CFG_MSB, GTYE3_CH_LOOP1_CFG_LSB) #define GTYE3_CH_LOOP2_CFG_ADDR 0x0108 #define GTYE3_CH_LOOP2_CFG_MSB 15 #define GTYE3_CH_LOOP2_CFG_LSB 0 #define GTYE3_CH_LOOP2_CFG_MASK BIT_MASK(GTYE3_CH_LOOP2_CFG_MSB, GTYE3_CH_LOOP2_CFG_LSB) #define GTYE3_CH_LOOP3_CFG_ADDR 0x0109 #define GTYE3_CH_LOOP3_CFG_MSB 15 #define GTYE3_CH_LOOP3_CFG_LSB 0 #define GTYE3_CH_LOOP3_CFG_MASK BIT_MASK(GTYE3_CH_LOOP3_CFG_MSB, GTYE3_CH_LOOP3_CFG_LSB) #define GTYE3_CH_LOOP4_CFG_ADDR 0x010A #define GTYE3_CH_LOOP4_CFG_MSB 15 #define GTYE3_CH_LOOP4_CFG_LSB 0 #define GTYE3_CH_LOOP4_CFG_MASK BIT_MASK(GTYE3_CH_LOOP4_CFG_MSB, GTYE3_CH_LOOP4_CFG_LSB) #define GTYE3_CH_LOOP5_CFG_ADDR 0x010B #define GTYE3_CH_LOOP5_CFG_MSB 15 #define GTYE3_CH_LOOP5_CFG_LSB 0 #define GTYE3_CH_LOOP5_CFG_MASK BIT_MASK(GTYE3_CH_LOOP5_CFG_MSB, GTYE3_CH_LOOP5_CFG_LSB) #define GTYE3_CH_LOOP6_CFG_ADDR 0x010C #define GTYE3_CH_LOOP6_CFG_MSB 15 #define GTYE3_CH_LOOP6_CFG_LSB 0 #define GTYE3_CH_LOOP6_CFG_MASK BIT_MASK(GTYE3_CH_LOOP6_CFG_MSB, GTYE3_CH_LOOP6_CFG_LSB) #define GTYE3_CH_LOOP7_CFG_ADDR 0x010D #define GTYE3_CH_LOOP7_CFG_MSB 15 #define GTYE3_CH_LOOP7_CFG_LSB 0 #define GTYE3_CH_LOOP7_CFG_MASK BIT_MASK(GTYE3_CH_LOOP7_CFG_MSB, GTYE3_CH_LOOP7_CFG_LSB) #define GTYE3_CH_LOOP8_CFG_ADDR 0x010E #define GTYE3_CH_LOOP8_CFG_MSB 15 #define GTYE3_CH_LOOP8_CFG_LSB 0 #define GTYE3_CH_LOOP8_CFG_MASK BIT_MASK(GTYE3_CH_LOOP8_CFG_MSB, GTYE3_CH_LOOP8_CFG_LSB) #define GTYE3_CH_LOOP9_CFG_ADDR 0x010F #define GTYE3_CH_LOOP9_CFG_MSB 15 #define GTYE3_CH_LOOP9_CFG_LSB 0 #define GTYE3_CH_LOOP9_CFG_MASK BIT_MASK(GTYE3_CH_LOOP9_CFG_MSB, GTYE3_CH_LOOP9_CFG_LSB) #define GTYE3_CH_LOOP10_CFG_ADDR 0x0110 #define GTYE3_CH_LOOP10_CFG_MSB 15 #define GTYE3_CH_LOOP10_CFG_LSB 0 #define GTYE3_CH_LOOP10_CFG_MASK BIT_MASK(GTYE3_CH_LOOP10_CFG_MSB, GTYE3_CH_LOOP10_CFG_LSB) #define GTYE3_CH_LOOP11_CFG_ADDR 0x0111 #define GTYE3_CH_LOOP11_CFG_MSB 15 #define GTYE3_CH_LOOP11_CFG_LSB 0 #define GTYE3_CH_LOOP11_CFG_MASK BIT_MASK(GTYE3_CH_LOOP11_CFG_MSB, GTYE3_CH_LOOP11_CFG_LSB) #define GTYE3_CH_LOOP12_CFG_ADDR 0x0112 #define GTYE3_CH_LOOP12_CFG_MSB 15 #define GTYE3_CH_LOOP12_CFG_LSB 0 #define GTYE3_CH_LOOP12_CFG_MASK BIT_MASK(GTYE3_CH_LOOP12_CFG_MSB, GTYE3_CH_LOOP12_CFG_LSB) #define GTYE3_CH_LOOP13_CFG_ADDR 0x0113 #define GTYE3_CH_LOOP13_CFG_MSB 15 #define GTYE3_CH_LOOP13_CFG_LSB 0 #define GTYE3_CH_LOOP13_CFG_MASK BIT_MASK(GTYE3_CH_LOOP13_CFG_MSB, GTYE3_CH_LOOP13_CFG_LSB) #define GTYE3_CH_CKCAL_RSVD0_ADDR 0x0114 #define GTYE3_CH_CKCAL_RSVD0_MSB 15 #define GTYE3_CH_CKCAL_RSVD0_LSB 0 #define GTYE3_CH_CKCAL_RSVD0_MASK BIT_MASK(GTYE3_CH_CKCAL_RSVD0_MSB, GTYE3_CH_CKCAL_RSVD0_LSB) #define GTYE3_CH_CKCAL_RSVD1_ADDR 0x0115 #define GTYE3_CH_CKCAL_RSVD1_MSB 15 #define GTYE3_CH_CKCAL_RSVD1_LSB 0 #define GTYE3_CH_CKCAL_RSVD1_MASK BIT_MASK(GTYE3_CH_CKCAL_RSVD1_MSB, GTYE3_CH_CKCAL_RSVD1_LSB) #define GTYE3_CH_CH_HSPMUX_ADDR 0x0116 #define GTYE3_CH_CH_HSPMUX_MSB 15 #define GTYE3_CH_CH_HSPMUX_LSB 0 #define GTYE3_CH_CH_HSPMUX_MASK BIT_MASK(GTYE3_CH_CH_HSPMUX_MSB, GTYE3_CH_CH_HSPMUX_LSB) #define GTYE3_CH_COMMA_ALIGN_LATENCY_ADDR 0x0250 #define GTYE3_CH_COMMA_ALIGN_LATENCY_MSB 6 #define GTYE3_CH_COMMA_ALIGN_LATENCY_LSB 0 #define GTYE3_CH_COMMA_ALIGN_LATENCY_MASK BIT_MASK(GTYE3_CH_COMMA_ALIGN_LATENCY_MSB, GTYE3_CH_COMMA_ALIGN_LATENCY_LSB) #define GTYE3_CH_ES_ERROR_COUNT_ADDR 0x0251 #define GTYE3_CH_ES_ERROR_COUNT_MSB 15 #define GTYE3_CH_ES_ERROR_COUNT_LSB 0 #define GTYE3_CH_ES_ERROR_COUNT_MASK BIT_MASK(GTYE3_CH_ES_ERROR_COUNT_MSB, GTYE3_CH_ES_ERROR_COUNT_LSB) #define GTYE3_CH_ES_SAMPLE_COUNT_ADDR 0x0252 #define GTYE3_CH_ES_SAMPLE_COUNT_MSB 15 #define GTYE3_CH_ES_SAMPLE_COUNT_LSB 0 #define GTYE3_CH_ES_SAMPLE_COUNT_MASK BIT_MASK(GTYE3_CH_ES_SAMPLE_COUNT_MSB, GTYE3_CH_ES_SAMPLE_COUNT_LSB) #define GTYE3_CH_ES_CONTROL_STATUS_ADDR 0x0253 #define GTYE3_CH_ES_CONTROL_STATUS_MSB 3 #define GTYE3_CH_ES_CONTROL_STATUS_LSB 0 #define GTYE3_CH_ES_CONTROL_STATUS_MASK BIT_MASK(GTYE3_CH_ES_CONTROL_STATUS_MSB, GTYE3_CH_ES_CONTROL_STATUS_LSB) #define GTYE3_CH_ES_RDATA_BYTE4_ADDR 0x0254 #define GTYE3_CH_ES_RDATA_BYTE4_MSB 15 #define GTYE3_CH_ES_RDATA_BYTE4_LSB 0 #define GTYE3_CH_ES_RDATA_BYTE4_MASK BIT_MASK(GTYE3_CH_ES_RDATA_BYTE4_MSB, GTYE3_CH_ES_RDATA_BYTE4_LSB) #define GTYE3_CH_ES_RDATA_BYTE3_ADDR 0x0255 #define GTYE3_CH_ES_RDATA_BYTE3_MSB 15 #define GTYE3_CH_ES_RDATA_BYTE3_LSB 0 #define GTYE3_CH_ES_RDATA_BYTE3_MASK BIT_MASK(GTYE3_CH_ES_RDATA_BYTE3_MSB, GTYE3_CH_ES_RDATA_BYTE3_LSB) #define GTYE3_CH_ES_RDATA_BYTE2_ADDR 0x0256 #define GTYE3_CH_ES_RDATA_BYTE2_MSB 15 #define GTYE3_CH_ES_RDATA_BYTE2_LSB 0 #define GTYE3_CH_ES_RDATA_BYTE2_MASK BIT_MASK(GTYE3_CH_ES_RDATA_BYTE2_MSB, GTYE3_CH_ES_RDATA_BYTE2_LSB) #define GTYE3_CH_ES_RDATA_BYTE1_ADDR 0x0257 #define GTYE3_CH_ES_RDATA_BYTE1_MSB 15 #define GTYE3_CH_ES_RDATA_BYTE1_LSB 0 #define GTYE3_CH_ES_RDATA_BYTE1_MASK BIT_MASK(GTYE3_CH_ES_RDATA_BYTE1_MSB, GTYE3_CH_ES_RDATA_BYTE1_LSB) #define GTYE3_CH_ES_RDATA_BYTE0_ADDR 0x0258 #define GTYE3_CH_ES_RDATA_BYTE0_MSB 15 #define GTYE3_CH_ES_RDATA_BYTE0_LSB 0 #define GTYE3_CH_ES_RDATA_BYTE0_MASK BIT_MASK(GTYE3_CH_ES_RDATA_BYTE0_MSB, GTYE3_CH_ES_RDATA_BYTE0_LSB) #define GTYE3_CH_ES_SDATA_BYTE4_ADDR 0x0259 #define GTYE3_CH_ES_SDATA_BYTE4_MSB 15 #define GTYE3_CH_ES_SDATA_BYTE4_LSB 0 #define GTYE3_CH_ES_SDATA_BYTE4_MASK BIT_MASK(GTYE3_CH_ES_SDATA_BYTE4_MSB, GTYE3_CH_ES_SDATA_BYTE4_LSB) #define GTYE3_CH_ES_SDATA_BYTE3_ADDR 0x025A #define GTYE3_CH_ES_SDATA_BYTE3_MSB 15 #define GTYE3_CH_ES_SDATA_BYTE3_LSB 0 #define GTYE3_CH_ES_SDATA_BYTE3_MASK BIT_MASK(GTYE3_CH_ES_SDATA_BYTE3_MSB, GTYE3_CH_ES_SDATA_BYTE3_LSB) #define GTYE3_CH_ES_SDATA_BYTE2_ADDR 0x025B #define GTYE3_CH_ES_SDATA_BYTE2_MSB 15 #define GTYE3_CH_ES_SDATA_BYTE2_LSB 0 #define GTYE3_CH_ES_SDATA_BYTE2_MASK BIT_MASK(GTYE3_CH_ES_SDATA_BYTE2_MSB, GTYE3_CH_ES_SDATA_BYTE2_LSB) #define GTYE3_CH_ES_SDATA_BYTE1_ADDR 0x025C #define GTYE3_CH_ES_SDATA_BYTE1_MSB 15 #define GTYE3_CH_ES_SDATA_BYTE1_LSB 0 #define GTYE3_CH_ES_SDATA_BYTE1_MASK BIT_MASK(GTYE3_CH_ES_SDATA_BYTE1_MSB, GTYE3_CH_ES_SDATA_BYTE1_LSB) #define GTYE3_CH_ES_SDATA_BYTE0_ADDR 0x025D #define GTYE3_CH_ES_SDATA_BYTE0_MSB 15 #define GTYE3_CH_ES_SDATA_BYTE0_LSB 0 #define GTYE3_CH_ES_SDATA_BYTE0_MASK BIT_MASK(GTYE3_CH_ES_SDATA_BYTE0_MSB, GTYE3_CH_ES_SDATA_BYTE0_LSB) #define GTYE3_CH_RX_PRBS_ERR_CNT_L_ADDR 0x025E #define GTYE3_CH_RX_PRBS_ERR_CNT_L_MSB 15 #define GTYE3_CH_RX_PRBS_ERR_CNT_L_LSB 0 #define GTYE3_CH_RX_PRBS_ERR_CNT_L_MASK BIT_MASK(GTYE3_CH_RX_PRBS_ERR_CNT_L_MSB, GTYE3_CH_RX_PRBS_ERR_CNT_L_LSB) #define GTYE3_CH_RX_PRBS_ERR_CNT_H_ADDR 0x025F #define GTYE3_CH_RX_PRBS_ERR_CNT_H_MSB 15 #define GTYE3_CH_RX_PRBS_ERR_CNT_H_LSB 0 #define GTYE3_CH_RX_PRBS_ERR_CNT_H_MASK BIT_MASK(GTYE3_CH_RX_PRBS_ERR_CNT_H_MSB, GTYE3_CH_RX_PRBS_ERR_CNT_H_LSB) #define GTYE3_CH_TXGBOX_FIFO_LATENCY_ADDR 0x0263 #define GTYE3_CH_TXGBOX_FIFO_LATENCY_MSB 15 #define GTYE3_CH_TXGBOX_FIFO_LATENCY_LSB 0 #define GTYE3_CH_TXGBOX_FIFO_LATENCY_MASK BIT_MASK(GTYE3_CH_TXGBOX_FIFO_LATENCY_MSB, GTYE3_CH_TXGBOX_FIFO_LATENCY_LSB) #define GTYE3_CH_RXGBOX_FIFO_LATENCY_ADDR 0x0269 #define GTYE3_CH_RXGBOX_FIFO_LATENCY_MSB 15 #define GTYE3_CH_RXGBOX_FIFO_LATENCY_LSB 0 #define GTYE3_CH_RXGBOX_FIFO_LATENCY_MASK BIT_MASK(GTYE3_CH_RXGBOX_FIFO_LATENCY_MSB, GTYE3_CH_RXGBOX_FIFO_LATENCY_LSB) #define GTYE3_CH_ES_SDATA_BYTE5_ADDR 0x0283 #define GTYE3_CH_ES_SDATA_BYTE5_MSB 15 #define GTYE3_CH_ES_SDATA_BYTE5_LSB 0 #define GTYE3_CH_ES_SDATA_BYTE5_MASK BIT_MASK(GTYE3_CH_ES_SDATA_BYTE5_MSB, GTYE3_CH_ES_SDATA_BYTE5_LSB) #define GTYE3_CH_ES_SDATA_BYTE6_ADDR 0x0284 #define GTYE3_CH_ES_SDATA_BYTE6_MSB 15 #define GTYE3_CH_ES_SDATA_BYTE6_LSB 0 #define GTYE3_CH_ES_SDATA_BYTE6_MASK BIT_MASK(GTYE3_CH_ES_SDATA_BYTE6_MSB, GTYE3_CH_ES_SDATA_BYTE6_LSB) #define GTYE3_CH_ES_SDATA_BYTE7_ADDR 0x0285 #define GTYE3_CH_ES_SDATA_BYTE7_MSB 15 #define GTYE3_CH_ES_SDATA_BYTE7_LSB 0 #define GTYE3_CH_ES_SDATA_BYTE7_MASK BIT_MASK(GTYE3_CH_ES_SDATA_BYTE7_MSB, GTYE3_CH_ES_SDATA_BYTE7_LSB) #define GTYE3_CH_ES_SDATA_BYTE8_ADDR 0x0286 #define GTYE3_CH_ES_SDATA_BYTE8_MSB 15 #define GTYE3_CH_ES_SDATA_BYTE8_LSB 0 #define GTYE3_CH_ES_SDATA_BYTE8_MASK BIT_MASK(GTYE3_CH_ES_SDATA_BYTE8_MSB, GTYE3_CH_ES_SDATA_BYTE8_LSB) #define GTYE3_CH_ES_SDATA_BYTE9_ADDR 0x0287 #define GTYE3_CH_ES_SDATA_BYTE9_MSB 15 #define GTYE3_CH_ES_SDATA_BYTE9_LSB 0 #define GTYE3_CH_ES_SDATA_BYTE9_MASK BIT_MASK(GTYE3_CH_ES_SDATA_BYTE9_MSB, GTYE3_CH_ES_SDATA_BYTE9_LSB) #define GTYE3_CH_ES_RDATA_BYTE5_ADDR 0x0288 #define GTYE3_CH_ES_RDATA_BYTE5_MSB 15 #define GTYE3_CH_ES_RDATA_BYTE5_LSB 0 #define GTYE3_CH_ES_RDATA_BYTE5_MASK BIT_MASK(GTYE3_CH_ES_RDATA_BYTE5_MSB, GTYE3_CH_ES_RDATA_BYTE5_LSB) #define GTYE3_CH_ES_RDATA_BYTE6_ADDR 0x0289 #define GTYE3_CH_ES_RDATA_BYTE6_MSB 15 #define GTYE3_CH_ES_RDATA_BYTE6_LSB 0 #define GTYE3_CH_ES_RDATA_BYTE6_MASK BIT_MASK(GTYE3_CH_ES_RDATA_BYTE6_MSB, GTYE3_CH_ES_RDATA_BYTE6_LSB) #define GTYE3_CH_ES_RDATA_BYTE7_ADDR 0x028A #define GTYE3_CH_ES_RDATA_BYTE7_MSB 15 #define GTYE3_CH_ES_RDATA_BYTE7_LSB 0 #define GTYE3_CH_ES_RDATA_BYTE7_MASK BIT_MASK(GTYE3_CH_ES_RDATA_BYTE7_MSB, GTYE3_CH_ES_RDATA_BYTE7_LSB) #define GTYE3_CH_ES_RDATA_BYTE8_ADDR 0x028B #define GTYE3_CH_ES_RDATA_BYTE8_MSB 15 #define GTYE3_CH_ES_RDATA_BYTE8_LSB 0 #define GTYE3_CH_ES_RDATA_BYTE8_MASK BIT_MASK(GTYE3_CH_ES_RDATA_BYTE8_MSB, GTYE3_CH_ES_RDATA_BYTE8_LSB) #define GTYE3_CH_ES_RDATA_BYTE9_ADDR 0x028C #define GTYE3_CH_ES_RDATA_BYTE9_MSB 15 #define GTYE3_CH_ES_RDATA_BYTE9_LSB 0 #define GTYE3_CH_ES_RDATA_BYTE9_MASK BIT_MASK(GTYE3_CH_ES_RDATA_BYTE9_MSB, GTYE3_CH_ES_RDATA_BYTE9_LSB) #endif /* GTYE3_REGS_H */