/* Copyright (c) 2014-2016 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Language: Verilog 2001 `timescale 1ns / 1ps /* * FPGA top-level module */ module fpga ( /* * Clock: 125MHz LVDS * Reset: Push button, active low */ input wire clk_125mhz_p, input wire clk_125mhz_n, input wire reset, /* * GPIO */ input wire btnu, input wire btnl, input wire btnd, input wire btnr, input wire btnc, input wire [3:0] sw, output wire [7:0] led, /* * Ethernet: 1000BASE-T SGMII */ input wire phy_sgmii_rx_p, input wire phy_sgmii_rx_n, output wire phy_sgmii_tx_p, output wire phy_sgmii_tx_n, input wire phy_sgmii_clk_p, input wire phy_sgmii_clk_n, output wire phy_reset_n, input wire phy_int_n, /* * UART: 500000 bps, 8N1 */ input wire uart_rxd, output wire uart_txd, output wire uart_rts, input wire uart_cts ); // Clock and reset wire clk_125mhz_ibufg; wire clk_125mhz_mmcm_out; // Internal 125 MHz clock wire clk_125mhz_int; wire rst_125mhz_int; wire mmcm_rst = reset; wire mmcm_locked; wire mmcm_clkfb; IBUFGDS #( .DIFF_TERM("FALSE"), .IBUF_LOW_PWR("FALSE") ) clk_125mhz_ibufg_inst ( .O (clk_125mhz_ibufg), .I (clk_125mhz_p), .IB (clk_125mhz_n) ); // MMCM instance // 125 MHz in, 125 MHz out // PFD range: 10 MHz to 500 MHz // VCO range: 600 MHz to 1440 MHz // M = 5, D = 1 sets Fvco = 625 MHz (in range) // Divide by 5 to get output frequency of 125 MHz MMCME3_BASE #( .BANDWIDTH("OPTIMIZED"), .CLKOUT0_DIVIDE_F(5), .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT0_PHASE(0), .CLKOUT1_DIVIDE(1), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT1_PHASE(0), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT2_PHASE(0), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.5), .CLKOUT3_PHASE(0), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.5), .CLKOUT4_PHASE(0), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.5), .CLKOUT5_PHASE(0), .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.5), .CLKOUT6_PHASE(0), .CLKFBOUT_MULT_F(5), .CLKFBOUT_PHASE(0), .DIVCLK_DIVIDE(1), .REF_JITTER1(0.010), .CLKIN1_PERIOD(8.0), .STARTUP_WAIT("FALSE"), .CLKOUT4_CASCADE("FALSE") ) clk_mmcm_inst ( .CLKIN1(clk_125mhz_ibufg), .CLKFBIN(mmcm_clkfb), .RST(mmcm_rst), .PWRDWN(1'b0), .CLKOUT0(clk_125mhz_mmcm_out), .CLKOUT0B(), .CLKOUT1(), .CLKOUT1B(), .CLKOUT2(), .CLKOUT2B(), .CLKOUT3(), .CLKOUT3B(), .CLKOUT4(), .CLKOUT5(), .CLKOUT6(), .CLKFBOUT(mmcm_clkfb), .CLKFBOUTB(), .LOCKED(mmcm_locked) ); BUFG clk_125mhz_bufg_inst ( .I(clk_125mhz_mmcm_out), .O(clk_125mhz_int) ); sync_reset #( .N(4) ) sync_reset_125mhz_inst ( .clk(clk_125mhz_int), .rst(~mmcm_locked), .sync_reset_out(rst_125mhz_int) ); // GPIO wire btnu_int; wire btnl_int; wire btnd_int; wire btnr_int; wire btnc_int; wire [3:0] sw_int; debounce_switch #( .WIDTH(9), .N(4), .RATE(125000) ) debounce_switch_inst ( .clk(clk_125mhz_int), .rst(rst_125mhz_int), .in({btnu, btnl, btnd, btnr, btnc, sw}), .out({btnu_int, btnl_int, btnd_int, btnr_int, btnc_int, sw_int}) ); wire uart_rxd_int; wire uart_cts_int; sync_signal #( .WIDTH(2), .N(2) ) sync_signal_inst ( .clk(clk_125mhz_int), .in({uart_rxd, uart_cts}), .out({uart_rxd_int, uart_cts_int}) ); // SGMII interface to PHY wire phy_gmii_clk_int; wire phy_gmii_rst_int; wire [7:0] phy_gmii_txd_int; wire phy_gmii_tx_en_int; wire phy_gmii_tx_er_int; wire [7:0] phy_gmii_rxd_int; wire phy_gmii_rx_dv_int; wire phy_gmii_rx_er_int; wire [15:0] status_vector; wire [4:0] pcspma_config_vector; assign pcspma_config_vector[4] = 1'b1; // autonegotiation enable assign pcspma_config_vector[3] = 1'b0; // isolate assign pcspma_config_vector[2] = 1'b0; // power down assign pcspma_config_vector[1] = 1'b0; // loopback enable assign pcspma_config_vector[0] = 1'b0; // unidirectional enable wire [15:0] pcspma_an_config_vector; assign pcspma_an_config_vector[15] = 1'b1; // SGMII link status assign pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge assign pcspma_an_config_vector[13:12] = 2'b01; // full duplex assign pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed assign pcspma_an_config_vector[9] = 1'b0; // reserved assign pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved assign pcspma_an_config_vector[6] = 1'b0; // reserved assign pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved assign pcspma_an_config_vector[4:1] = 4'b0000; // reserved assign pcspma_an_config_vector[0] = 1'b1; // SGMII gig_ethernet_pcs_pma_0 eth_pcspma ( // SGMII .txp (phy_sgmii_tx_p), .txn (phy_sgmii_tx_n), .rxp (phy_sgmii_rx_p), .rxn (phy_sgmii_rx_n), // Ref clock from PHY .refclk625_p (phy_sgmii_clk_p), .refclk625_n (phy_sgmii_clk_n), // async reset .reset (rst_125mhz_int), // clock and reset outputs .clk125_out (phy_gmii_clk_int), .clk625_out (), .clk312_out (), .rst_125_out (phy_gmii_rst_int), .idelay_rdy_out (), .mmcm_locked_out (), // MAC clocking .sgmii_clk_r (), .sgmii_clk_f (), .sgmii_clk_en (), // need to pass through to MAC // Speed control .speed_is_10_100 (1'b0), .speed_is_100 (1'b0), // Internal GMII .gmii_txd (phy_gmii_txd_int), .gmii_tx_en (phy_gmii_tx_en_int), .gmii_tx_er (phy_gmii_tx_er_int), .gmii_rxd (phy_gmii_rxd_int), .gmii_rx_dv (phy_gmii_rx_dv_int), .gmii_rx_er (phy_gmii_rx_er_int), .gmii_isolate (), // Configuration .configuration_vector (pcspma_config_vector), .an_interrupt (), .an_adv_config_vector (pcspma_an_config_vector), .an_restart_config (1'b0), // Status .status_vector (status_vector), .signal_detect (1'b1) ); wire [7:0] led_int; // SGMII interface debug: // SW12:4 (sw[0]) off for payload byte, on for status vector // SW12:3 (sw[1]) off for LSB of status vector, on for MSB assign led = sw[0] ? (sw[1] ? status_vector[15:8] : status_vector[7:0]) : led_int; fpga_core core_inst ( /* * Clock: 125MHz * Synchronous reset */ .clk(clk_125mhz_int), .rst(rst_125mhz_int), /* * GPIO */ .btnu(btnu_int), .btnl(btnl_int), .btnd(btnd_int), .btnr(btnr_int), .btnc(btnc_int), .sw(sw_int), .led(led_int), /* * Ethernet: 1000BASE-T SGMII */ .phy_gmii_clk(phy_gmii_clk_int), .phy_gmii_rst(phy_gmii_rst_int), .phy_gmii_rxd(phy_gmii_rxd_int), .phy_gmii_rx_dv(phy_gmii_rx_dv_int), .phy_gmii_rx_er(phy_gmii_rx_er_int), .phy_gmii_txd(phy_gmii_txd_int), .phy_gmii_tx_en(phy_gmii_tx_en_int), .phy_gmii_tx_er(phy_gmii_tx_er_int), .phy_reset_n(phy_reset_n), .phy_int_n(phy_int_n), /* * UART: 115200 bps, 8N1 */ .uart_rxd(uart_rxd_int), .uart_txd(uart_txd), .uart_rts(uart_rts), .uart_cts(uart_cts_int) ); endmodule