.. _mod_mqnic_l2_ingress: ==================== ``mqnic_l2_ingress`` ==================== ``mqnic_l2_ingress`` contains layer 2 ingress processing components, and operates synchronous to the MAC RX clock. Currently, this module is a placeholder, passing through streaming data without modification. Parameters ========== .. object:: AXIS_DATA_WIDTH Streaming interface ``tdata`` signal width, default ``512``. .. object:: AXIS_KEEP_WIDTH Streaming interface ``tkeep`` signal width, must be set to ``AXIS_DATA_WIDTH/8``. .. object:: AXIS_USER_WIDTH Streaming interface ``tuser`` signal width, default ``1``. .. object:: AXIS_USE_READY Use ``tready`` signal, default ``0``. If set, logic will exert backpressure with ``tready`` instead of dropping packets when RX FIFOs are full. Ports ===== .. object:: clk Logic clock. .. table:: ====== === ===== ================== Signal Dir Width Description ====== === ===== ================== clk in 1 Logic clock ====== === ===== ================== .. object:: rst Logic reset, active high .. table:: ====== === ===== ================== Signal Dir Width Description ====== === ===== ================== rst in 1 Logic reset, active high ====== === ===== ================== .. object:: s_axis Streaming receive data from network .. table:: ============= === =============== ================== Signal Dir Width Description ============= === =============== ================== s_axis_tdata in AXIS_DATA_WIDTH Streaming data s_axis_tkeep in AXIS_KEEP_WIDTH Byte enable s_axis_tvalid in Data valid s_axis_tready out Ready for data s_axis_tlast in End of frame s_axis_tuser in AXIS_USER_WIDTH Sideband data ============= === =============== ================== ``s_axis_tuser`` bits .. table:: ============== ========= ============ ============= Bit Name Width Description ============== ========= ============ ============= 0 bad_frame 1 Invalid frame PTP_TS_WIDTH:1 ptp_ts PTP_TS_WIDTH PTP timestamp ============== ========= ============ ============= .. object:: m_axis Streaming receive data towards host .. table:: ============= === =============== ================== Signal Dir Width Description ============= === =============== ================== m_axis_tdata out AXIS_DATA_WIDTH Streaming data m_axis_tkeep out AXIS_KEEP_WIDTH Byte enable m_axis_tvalid out Data valid m_axis_tready in Ready for data m_axis_tlast out End of frame m_axis_tuser out AXIS_USER_WIDTH Sideband data ============= === =============== ================== ``m_axis_tuser`` bits .. table:: ============== ========= ============ ============= Bit Name Width Description ============== ========= ============ ============= 0 bad_frame 1 Invalid frame PTP_TS_WIDTH:1 ptp_ts PTP_TS_WIDTH PTP timestamp ============== ========= ============ =============