# SPDX-License-Identifier: BSD-2-Clause-Views # Copyright (c) 2020-2023 The Regents of the University of California TOPLEVEL_LANG = verilog SIM ?= icarus WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps DUT = tdma_ber TOPLEVEL = $(DUT) MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/tdma_ber_ch.v VERILOG_SOURCES += ../../rtl/tdma_scheduler.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v # module parameters export PARAM_COUNT := 2 export PARAM_INDEX_WIDTH := 6 export PARAM_SLICE_WIDTH := 5 export PARAM_AXIL_DATA_WIDTH := 32 export PARAM_AXIL_ADDR_WIDTH := $(shell python -c "print($(PARAM_INDEX_WIDTH)+4+1+($(PARAM_COUNT)-1).bit_length())") export PARAM_AXIL_STRB_WIDTH := $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 ) export PARAM_SCHEDULE_START_S := 0 export PARAM_SCHEDULE_START_NS := 0 export PARAM_SCHEDULE_PERIOD_S := 0 export PARAM_SCHEDULE_PERIOD_NS := 1000000 export PARAM_TIMESLOT_PERIOD_S := 0 export PARAM_TIMESLOT_PERIOD_NS := 100000 export PARAM_ACTIVE_PERIOD_S := 0 export PARAM_ACTIVE_PERIOD_NS := 100000 export PARAM_PHY_PIPELINE := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) VERILOG_SOURCES += iverilog_dump.v COMPILE_ARGS += -s iverilog_dump endif else ifeq ($(SIM), verilator) COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) ifeq ($(WAVES), 1) COMPILE_ARGS += --trace-fst endif endif include $(shell cocotb-config --makefiles)/Makefile.sim iverilog_dump.v: echo 'module iverilog_dump();' > $@ echo 'initial begin' >> $@ echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ echo 'end' >> $@ echo 'endmodule' >> $@ clean:: @rm -rf iverilog_dump.v @rm -rf dump.fst $(TOPLEVEL).fst